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02d711b93e
instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
805 B
LLVM
23 lines
805 B
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep frest %t1.s | count 2
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; RUN: grep -w fi %t1.s | count 2
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; RUN: grep -w fm %t1.s | count 2
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; RUN: grep fma %t1.s | count 2
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; RUN: grep fnms %t1.s | count 4
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; RUN: grep cgti %t1.s | count 2
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; RUN: grep selb %t1.s | count 2
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;
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; This file includes standard floating point arithmetic instructions
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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define float @fdiv32(float %arg1, float %arg2) {
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%A = fdiv float %arg1, %arg2
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ret float %A
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}
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define <4 x float> @fdiv_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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%A = fdiv <4 x float> %arg1, %arg2
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ret <4 x float> %A
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}
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