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https://github.com/c64scene-ar/llvm-6502.git
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ae1ae2c3a1
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632 91177308-0d34-0410-b5e6-96231b3b80d8
457 lines
21 KiB
C++
457 lines
21 KiB
C++
//===- llvm/Analysis/TargetTransformInfo.h ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass exposes codegen information to IR-level passes. Every
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// transformation that uses codegen information is broken into three parts:
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// 1. The IR-level analysis pass.
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// 2. The IR-level transformation interface which provides the needed
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// information.
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// 3. Codegen-level implementation which uses target-specific hooks.
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//
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// This file defines #2, which is the interface that IR-level transformations
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// use for querying the codegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
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#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class Function;
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class GlobalValue;
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class Loop;
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class Type;
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class User;
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class Value;
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/// TargetTransformInfo - This pass provides access to the codegen
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/// interfaces that are needed for IR-level transformations.
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class TargetTransformInfo {
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protected:
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/// \brief The TTI instance one level down the stack.
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///
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/// This is used to implement the default behavior all of the methods which
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/// is to delegate up through the stack of TTIs until one can answer the
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/// query.
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TargetTransformInfo *PrevTTI;
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/// \brief The top of the stack of TTI analyses available.
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///
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/// This is a convenience routine maintained as TTI analyses become available
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/// that complements the PrevTTI delegation chain. When one part of an
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/// analysis pass wants to query another part of the analysis pass it can use
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/// this to start back at the top of the stack.
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TargetTransformInfo *TopTTI;
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/// All pass subclasses must in their initializePass routine call
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/// pushTTIStack with themselves to update the pointers tracking the previous
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/// TTI instance in the analysis group's stack, and the top of the analysis
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/// group's stack.
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void pushTTIStack(Pass *P);
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/// All pass subclasses must call TargetTransformInfo::getAnalysisUsage.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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public:
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/// This class is intended to be subclassed by real implementations.
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virtual ~TargetTransformInfo() = 0;
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/// \name Generic Target Information
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/// @{
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/// \brief Underlying constants for 'cost' values in this interface.
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///
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/// Many APIs in this interface return a cost. This enum defines the
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/// fundamental values that should be used to interpret (and produce) those
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/// costs. The costs are returned as an unsigned rather than a member of this
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/// enumeration because it is expected that the cost of one IR instruction
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/// may have a multiplicative factor to it or otherwise won't fit directly
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/// into the enum. Moreover, it is common to sum or average costs which works
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/// better as simple integral values. Thus this enum only provides constants.
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///
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/// Note that these costs should usually reflect the intersection of code-size
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/// cost and execution cost. A free instruction is typically one that folds
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/// into another instruction. For example, reg-to-reg moves can often be
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/// skipped by renaming the registers in the CPU, but they still are encoded
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/// and thus wouldn't be considered 'free' here.
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enum TargetCostConstants {
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TCC_Free = 0, ///< Expected to fold away in lowering.
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TCC_Basic = 1, ///< The cost of a typical 'add' instruction.
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TCC_Expensive = 4 ///< The cost of a 'div' instruction on x86.
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};
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/// \brief Estimate the cost of a specific operation when lowered.
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///
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/// Note that this is designed to work on an arbitrary synthetic opcode, and
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/// thus work for hypothetical queries before an instruction has even been
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/// formed. However, this does *not* work for GEPs, and must not be called
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/// for a GEP instruction. Instead, use the dedicated getGEPCost interface as
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/// analyzing a GEP's cost required more information.
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///
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/// Typically only the result type is required, and the operand type can be
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/// omitted. However, if the opcode is one of the cast instructions, the
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/// operand type is required.
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///
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/// The returned cost is defined in terms of \c TargetCostConstants, see its
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/// comments for a detailed explanation of the cost values.
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virtual unsigned getOperationCost(unsigned Opcode, Type *Ty,
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Type *OpTy = nullptr) const;
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/// \brief Estimate the cost of a GEP operation when lowered.
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///
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/// The contract for this function is the same as \c getOperationCost except
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/// that it supports an interface that provides extra information specific to
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/// the GEP operation.
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virtual unsigned getGEPCost(const Value *Ptr,
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ArrayRef<const Value *> Operands) const;
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/// \brief Estimate the cost of a function call when lowered.
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///
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/// The contract for this is the same as \c getOperationCost except that it
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/// supports an interface that provides extra information specific to call
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/// instructions.
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///
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/// This is the most basic query for estimating call cost: it only knows the
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/// function type and (potentially) the number of arguments at the call site.
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/// The latter is only interesting for varargs function types.
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virtual unsigned getCallCost(FunctionType *FTy, int NumArgs = -1) const;
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/// \brief Estimate the cost of calling a specific function when lowered.
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///
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/// This overload adds the ability to reason about the particular function
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/// being called in the event it is a library call with special lowering.
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virtual unsigned getCallCost(const Function *F, int NumArgs = -1) const;
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/// \brief Estimate the cost of calling a specific function when lowered.
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///
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/// This overload allows specifying a set of candidate argument values.
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virtual unsigned getCallCost(const Function *F,
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ArrayRef<const Value *> Arguments) const;
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/// \brief Estimate the cost of an intrinsic when lowered.
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///
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/// Mirrors the \c getCallCost method but uses an intrinsic identifier.
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virtual unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
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ArrayRef<Type *> ParamTys) const;
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/// \brief Estimate the cost of an intrinsic when lowered.
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///
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/// Mirrors the \c getCallCost method but uses an intrinsic identifier.
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virtual unsigned getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
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ArrayRef<const Value *> Arguments) const;
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/// \brief Estimate the cost of a given IR user when lowered.
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///
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/// This can estimate the cost of either a ConstantExpr or Instruction when
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/// lowered. It has two primary advantages over the \c getOperationCost and
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/// \c getGEPCost above, and one significant disadvantage: it can only be
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/// used when the IR construct has already been formed.
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///
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/// The advantages are that it can inspect the SSA use graph to reason more
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/// accurately about the cost. For example, all-constant-GEPs can often be
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/// folded into a load or other instruction, but if they are used in some
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/// other context they may not be folded. This routine can distinguish such
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/// cases.
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///
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/// The returned cost is defined in terms of \c TargetCostConstants, see its
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/// comments for a detailed explanation of the cost values.
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virtual unsigned getUserCost(const User *U) const;
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/// \brief hasBranchDivergence - Return true if branch divergence exists.
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/// Branch divergence has a significantly negative impact on GPU performance
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/// when threads in the same wavefront take different paths due to conditional
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/// branches.
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virtual bool hasBranchDivergence() const;
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/// \brief Test whether calls to a function lower to actual program function
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/// calls.
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///
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/// The idea is to test whether the program is likely to require a 'call'
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/// instruction or equivalent in order to call the given function.
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///
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/// FIXME: It's not clear that this is a good or useful query API. Client's
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/// should probably move to simpler cost metrics using the above.
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/// Alternatively, we could split the cost interface into distinct code-size
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/// and execution-speed costs. This would allow modelling the core of this
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/// query more accurately as a call is a single small instruction, but
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/// incurs significant execution cost.
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virtual bool isLoweredToCall(const Function *F) const;
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/// Parameters that control the generic loop unrolling transformation.
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struct UnrollingPreferences {
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/// The cost threshold for the unrolled loop, compared to
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/// CodeMetrics.NumInsts aggregated over all basic blocks in the loop body.
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/// The unrolling factor is set such that the unrolled loop body does not
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/// exceed this cost. Set this to UINT_MAX to disable the loop body cost
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/// restriction.
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unsigned Threshold;
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/// The cost threshold for the unrolled loop when optimizing for size (set
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/// to UINT_MAX to disable).
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unsigned OptSizeThreshold;
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/// The cost threshold for the unrolled loop, like Threshold, but used
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/// for partial/runtime unrolling (set to UINT_MAX to disable).
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unsigned PartialThreshold;
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/// The cost threshold for the unrolled loop when optimizing for size, like
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/// OptSizeThreshold, but used for partial/runtime unrolling (set to UINT_MAX
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/// to disable).
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unsigned PartialOptSizeThreshold;
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/// A forced unrolling factor (the number of concatenated bodies of the
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/// original loop in the unrolled loop body). When set to 0, the unrolling
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/// transformation will select an unrolling factor based on the current cost
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/// threshold and other factors.
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unsigned Count;
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// Set the maximum unrolling factor. The unrolling factor may be selected
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// using the appropriate cost threshold, but may not exceed this number
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// (set to UINT_MAX to disable). This does not apply in cases where the
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// loop is being fully unrolled.
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unsigned MaxCount;
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/// Allow partial unrolling (unrolling of loops to expand the size of the
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/// loop body, not only to eliminate small constant-trip-count loops).
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bool Partial;
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/// Allow runtime unrolling (unrolling of loops to expand the size of the
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/// loop body even when the number of loop iterations is not known at compile
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/// time).
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bool Runtime;
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};
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/// \brief Get target-customized preferences for the generic loop unrolling
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/// transformation. The caller will initialize UP with the current
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/// target-independent defaults.
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virtual void getUnrollingPreferences(const Function *F, Loop *L,
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UnrollingPreferences &UP) const;
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/// @}
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/// \name Scalar Target Information
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/// @{
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/// \brief Flags indicating the kind of support for population count.
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///
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/// Compared to the SW implementation, HW support is supposed to
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/// significantly boost the performance when the population is dense, and it
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/// may or may not degrade performance if the population is sparse. A HW
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/// support is considered as "Fast" if it can outperform, or is on a par
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/// with, SW implementation when the population is sparse; otherwise, it is
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/// considered as "Slow".
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enum PopcntSupportKind {
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PSK_Software,
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PSK_SlowHardware,
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PSK_FastHardware
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};
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/// \brief Return true if the specified immediate is legal add immediate, that
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/// is the target has add instructions which can add a register with the
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/// immediate without having to materialize the immediate into a register.
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virtual bool isLegalAddImmediate(int64_t Imm) const;
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/// \brief Return true if the specified immediate is legal icmp immediate,
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/// that is the target has icmp instructions which can compare a register
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/// against the immediate without having to materialize the immediate into a
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/// register.
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virtual bool isLegalICmpImmediate(int64_t Imm) const;
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/// \brief Return true if the addressing mode represented by AM is legal for
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/// this target, for a load/store of the specified type.
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/// The type may be VoidTy, in which case only return true if the addressing
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/// mode is legal for a load/store of any legal type.
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/// TODO: Handle pre/postinc as well.
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virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
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int64_t BaseOffset, bool HasBaseReg,
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int64_t Scale) const;
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/// \brief Return true if the target works with masked instruction
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/// AVX2 allows masks for consecutive load and store for i32 and i64 elements.
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/// AVX-512 architecture will also allow masks for non-consecutive memory
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/// accesses.
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virtual bool isLegalPredicatedStore(Type *DataType, int Consecutive) const;
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virtual bool isLegalPredicatedLoad (Type *DataType, int Consecutive) const;
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/// \brief Return the cost of the scaling factor used in the addressing
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/// mode represented by AM for this target, for a load/store
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/// of the specified type.
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/// If the AM is supported, the return value must be >= 0.
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/// If the AM is not supported, it returns a negative value.
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/// TODO: Handle pre/postinc as well.
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virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
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int64_t BaseOffset, bool HasBaseReg,
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int64_t Scale) const;
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/// \brief Return true if it's free to truncate a value of type Ty1 to type
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/// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
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/// by referencing its sub-register AX.
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virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
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/// \brief Return true if this type is legal.
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virtual bool isTypeLegal(Type *Ty) const;
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/// \brief Returns the target's jmp_buf alignment in bytes.
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virtual unsigned getJumpBufAlignment() const;
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/// \brief Returns the target's jmp_buf size in bytes.
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virtual unsigned getJumpBufSize() const;
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/// \brief Return true if switches should be turned into lookup tables for the
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/// target.
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virtual bool shouldBuildLookupTables() const;
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/// \brief Return hardware support for population count.
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virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
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/// \brief Return true if the hardware has a fast square-root instruction.
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virtual bool haveFastSqrt(Type *Ty) const;
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/// \brief Return the expected cost of materializing for the given integer
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/// immediate of the specified type.
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virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
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/// \brief Return the expected cost of materialization for the given integer
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/// immediate of the specified type for a given instruction. The cost can be
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/// zero if the immediate can be folded into the specified instruction.
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virtual unsigned getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
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Type *Ty) const;
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virtual unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty) const;
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/// @}
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/// \name Vector Target Information
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/// @{
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/// \brief The various kinds of shuffle patterns for vector queries.
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enum ShuffleKind {
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SK_Broadcast, ///< Broadcast element 0 to all other elements.
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SK_Reverse, ///< Reverse the order of the vector.
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SK_Alternate, ///< Choose alternate elements from vector.
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SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.
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SK_ExtractSubvector ///< ExtractSubvector Index indicates start offset.
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};
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/// \brief Additional information about an operand's possible values.
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enum OperandValueKind {
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OK_AnyValue, // Operand can have any value.
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OK_UniformValue, // Operand is uniform (splat of a value).
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OK_UniformConstantValue, // Operand is uniform constant.
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OK_NonUniformConstantValue // Operand is a non uniform constant value.
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};
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/// \brief Additional properties of an operand's values.
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enum OperandValueProperties { OP_None = 0, OP_PowerOf2 = 1 };
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/// \return The number of scalar or vector registers that the target has.
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/// If 'Vectors' is true, it returns the number of vector registers. If it is
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/// set to false, it returns the number of scalar registers.
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virtual unsigned getNumberOfRegisters(bool Vector) const;
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/// \return The width of the largest scalar or vector register type.
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virtual unsigned getRegisterBitWidth(bool Vector) const;
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/// \return The maximum interleave factor that any transform should try to
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/// perform for this target. This number depends on the level of parallelism
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/// and the number of execution units in the CPU.
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virtual unsigned getMaxInterleaveFactor() const;
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/// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
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virtual unsigned
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getArithmeticInstrCost(unsigned Opcode, Type *Ty,
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OperandValueKind Opd1Info = OK_AnyValue,
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OperandValueKind Opd2Info = OK_AnyValue,
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OperandValueProperties Opd1PropInfo = OP_None,
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OperandValueProperties Opd2PropInfo = OP_None) const;
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/// \return The cost of a shuffle instruction of kind Kind and of type Tp.
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/// The index and subtype parameters are used by the subvector insertion and
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/// extraction shuffle kinds.
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virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, int Index = 0,
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Type *SubTp = nullptr) const;
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/// \return The expected cost of cast instructions, such as bitcast, trunc,
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/// zext, etc.
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virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const;
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/// \return The expected cost of control-flow related instructions such as
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/// Phi, Ret, Br.
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virtual unsigned getCFInstrCost(unsigned Opcode) const;
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/// \returns The expected cost of compare and select instructions.
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virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy = nullptr) const;
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/// \return The expected cost of vector Insert and Extract.
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/// Use -1 to indicate that there is no information on the index value.
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virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index = -1) const;
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/// \return The cost of Load and Store instructions.
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virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
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unsigned Alignment,
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unsigned AddressSpace) const;
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/// \brief Calculate the cost of performing a vector reduction.
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///
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/// This is the cost of reducing the vector value of type \p Ty to a scalar
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/// value using the operation denoted by \p Opcode. The form of the reduction
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/// can either be a pairwise reduction or a reduction that splits the vector
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/// at every reduction level.
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///
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/// Pairwise:
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/// (v0, v1, v2, v3)
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/// ((v0+v1), (v2, v3), undef, undef)
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/// Split:
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/// (v0, v1, v2, v3)
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/// ((v0+v2), (v1+v3), undef, undef)
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virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
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bool IsPairwiseForm) const;
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/// \returns The cost of Intrinsic instructions.
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virtual unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Type *> Tys) const;
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/// \returns The number of pieces into which the provided type must be
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/// split during legalization. Zero is returned when the answer is unknown.
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virtual unsigned getNumberOfParts(Type *Tp) const;
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/// \returns The cost of the address computation. For most targets this can be
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/// merged into the instruction indexing mode. Some targets might want to
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/// distinguish between address computation for memory operations on vector
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/// types and scalar types. Such targets should override this function.
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/// The 'IsComplex' parameter is a hint that the address computation is likely
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/// to involve multiple instructions and as such unlikely to be merged into
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/// the address indexing mode.
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virtual unsigned getAddressComputationCost(Type *Ty,
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bool IsComplex = false) const;
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/// \returns The cost, if any, of keeping values of the given types alive
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/// over a callsite.
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///
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/// Some types may require the use of register classes that do not have
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/// any callee-saved registers, so would require a spill and fill.
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virtual unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type*> Tys) const;
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/// @}
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/// Analysis group identification.
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static char ID;
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};
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/// \brief Create the base case instance of a pass in the TTI analysis group.
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///
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/// This class provides the base case for the stack of TTI analyzes. It doesn't
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/// delegate to anything and uses the STTI and VTTI objects passed in to
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/// satisfy the queries.
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ImmutablePass *createNoTargetTransformInfoPass();
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} // End llvm namespace
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#endif
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