mirror of
https://github.com/c64scene-ar/llvm-6502.git
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dfe076af98
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
248 lines
10 KiB
C++
248 lines
10 KiB
C++
//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that AArch64 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H
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#define LLVM_TARGET_AARCH64_ISELLOWERING_H
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace AArch64ISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// This is a conditional branch which also notes the flag needed
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// (eq/sgt/...). A64 puts this information on the branches rather than
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// compares as LLVM does.
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BR_CC,
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// A node to be selected to an actual call operation: either BL or BLR in
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// the absence of tail calls.
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Call,
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// Indicates a floating-point immediate which fits into the format required
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// by the FMOV instructions. First (and only) operand is the 8-bit encoded
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// value of that immediate.
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FPMOV,
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// Corresponds directly to an EXTR instruction. Operands are an LHS an RHS
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// and an LSB.
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EXTR,
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// Wraps a load from the GOT, which should always be performed with a 64-bit
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// load instruction. This prevents the DAG combiner folding a truncate to
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// form a smaller memory access.
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GOTLoad,
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// Performs a bitfield insert. Arguments are: the value being inserted into;
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// the value being inserted; least significant bit changed; width of the
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// field.
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BFI,
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// Simply a convenient node inserted during ISelLowering to represent
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// procedure return. Will almost certainly be selected to "RET".
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Ret,
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/// Extracts a field of contiguous bits from the source and sign extends
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/// them into a single register. Arguments are: source; immr; imms. Note
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/// these are pre-encoded since DAG matching can't cope with combining LSB
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/// and Width into these values itself.
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SBFX,
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/// This is an A64-ification of the standard LLVM SELECT_CC operation. The
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/// main difference is that it only has the values and an A64 condition,
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/// which will be produced by a setcc instruction.
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SELECT_CC,
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/// This serves most of the functions of the LLVM SETCC instruction, for two
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/// purposes. First, it prevents optimisations from fiddling with the
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/// compare after we've moved the CondCode information onto the SELECT_CC or
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/// BR_CC instructions. Second, it gives a legal instruction for the actual
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/// comparison.
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///
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/// It keeps a record of the condition flags asked for because certain
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/// instructions are only valid for a subset of condition codes.
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SETCC,
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// Designates a node which is a tail call: both a call and a return
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// instruction as far as selction is concerned. It should be selected to an
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// unconditional branch. Has the usual plethora of call operands, but: 1st
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// is callee, 2nd is stack adjustment required immediately before branch.
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TC_RETURN,
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// Designates a call used to support the TLS descriptor ABI. The call itself
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// will be indirect ("BLR xN") but a relocation-specifier (".tlsdesccall
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// var") must be attached somehow during code generation. It takes two
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// operands: the callee and the symbol to be relocated against.
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TLSDESCCALL,
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// Leaf node which will be lowered to an appropriate MRS to obtain the
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// thread pointer: TPIDR_EL0.
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THREAD_POINTER,
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/// Extracts a field of contiguous bits from the source and zero extends
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/// them into a single register. Arguments are: source; immr; imms. Note
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/// these are pre-encoded since DAG matching can't cope with combining LSB
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/// and Width into these values itself.
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UBFX,
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// Wraps an address which the ISelLowering phase has decided should be
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// created using the small absolute memory model: i.e. adrp/add or
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// adrp/mem-op. This exists to prevent bare TargetAddresses which may never
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// get selected.
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WrapperSmall
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};
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}
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class AArch64Subtarget;
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class AArch64TargetMachine;
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class AArch64TargetLowering : public TargetLowering {
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public:
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explicit AArch64TargetLowering(AArch64TargetMachine &TM);
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const char *getTargetNodeName(unsigned Opcode) const;
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CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
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SDValue LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
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DebugLoc DL, SDValue &Chain) const;
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization. Targets which want to do tail call
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/// optimization should implement this function.
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bool IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC,
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bool IsVarArg,
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bool IsCalleeStructRet,
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bool IsCallerStructRet,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const;
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/// Finds the incoming stack arguments which overlap the given fixed stack
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/// object and incorporates their load into the current chain. This prevents
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/// an upcoming store from clobbering the stack argument before it's used.
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SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
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MachineFrameInfo *MFI, int ClobberedFI) const;
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EVT getSetCCResultType(EVT VT) const;
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bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
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bool IsTailCallConvention(CallingConv::ID CallCC) const;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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bool isLegalICmpImmediate(int64_t Val) const;
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SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &A64cc, SelectionDAG &DAG, DebugLoc &dl) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
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MachineBasicBlock *
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emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
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unsigned Size, unsigned Opcode) const;
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MachineBasicBlock *
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emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size, unsigned CmpOp,
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A64CC::CondCodes Cond) const;
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MachineBasicBlock *
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emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size) const;
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MachineBasicBlock *
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EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
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RTLIB::Libcall Call) const;
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SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
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SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, DebugLoc DL,
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SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
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/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
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/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
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/// is expanded to mul + add.
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virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
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ConstraintType getConstraintType(const std::string &Constraint) const;
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ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info,
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const char *Constraint) const;
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void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
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private:
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const AArch64Subtarget *Subtarget;
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const TargetRegisterInfo *RegInfo;
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const InstrItineraryData *Itins;
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};
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} // namespace llvm
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#endif // LLVM_TARGET_AARCH64_ISELLOWERING_H
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