llvm-6502/test/CodeGen/Mips/mips64countleading.ll
Akira Hatanaka c79507a4dd Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
case for DCLO and DCLZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:20:27 +00:00

20 lines
421 B
LLVM

; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i64 @t1(i64 %X) nounwind readnone {
entry:
; CHECK: dclz
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i64 @t3(i64 %X) nounwind readnone {
entry:
; CHECK: dclo
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
}