llvm-6502/lib/Target/Mips
2013-06-24 10:05:34 +00:00
..
AsmParser This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. 2013-06-24 10:05:34 +00:00
Disassembler Remove the Copied parameter from MemoryObject::readBytes. 2013-05-24 10:54:58 +00:00
InstPrinter
MCTargetDesc Mips ELF: Mark object file as ABI compliant 2013-06-18 19:47:15 +00:00
TargetInfo
CMakeLists.txt Fix CMakeLists. 2013-06-11 22:36:30 +00:00
LLVMBuild.txt
Makefile
MicroMipsInstrFormats.td
MicroMipsInstrInfo.td
Mips16FrameLowering.cpp Use pointers to the MCAsmInfo and MCRegInfo. 2013-06-18 07:20:20 +00:00
Mips16FrameLowering.h
Mips16HardFloat.cpp
Mips16HardFloat.h
Mips16InstrFormats.td
Mips16InstrInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
Mips16InstrInfo.h
Mips16InstrInfo.td
Mips16ISelDAGToDAG.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 21:36:55 +00:00
Mips16ISelDAGToDAG.h Track IR ordering of SelectionDAG nodes 2/4. 2013-05-25 02:42:55 +00:00
Mips16ISelLowering.cpp Mips: Remove global set. 2013-06-13 19:06:52 +00:00
Mips16ISelLowering.h Mips: Remove global set. 2013-06-13 19:06:52 +00:00
Mips16RegisterInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
Mips16RegisterInfo.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
Mips64InstrInfo.td [mips] Add instruction selection patterns for blez and bgez. 2013-05-21 17:13:47 +00:00
Mips.h [mips] Add an IR transformation pass that optimizes calls to sqrt. 2013-06-11 22:21:44 +00:00
Mips.td
MipsAnalyzeImmediate.cpp Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. 2013-05-24 22:23:49 +00:00
MipsAnalyzeImmediate.h
MipsAsmPrinter.cpp Mips ELF: Mark object file as ABI compliant 2013-06-18 19:47:15 +00:00
MipsAsmPrinter.h DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
MipsCallingConv.td
MipsCodeEmitter.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
MipsCondMov.td
MipsConstantIslandPass.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
MipsDelaySlotFiller.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
MipsDSPInstrFormats.td
MipsDSPInstrInfo.td
MipsFrameLowering.cpp
MipsFrameLowering.h
MipsInstrFormats.td [mips] Trap on integer division by zero. 2013-05-20 18:07:43 +00:00
MipsInstrFPU.td This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. 2013-06-24 10:05:34 +00:00
MipsInstrInfo.cpp DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
MipsInstrInfo.h DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
MipsInstrInfo.td [mips] brcond + setgt/setugt instruction selection patterns. 2013-06-05 19:49:55 +00:00
MipsISelDAGToDAG.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 21:36:55 +00:00
MipsISelDAGToDAG.h
MipsISelLowering.cpp The getRegForInlineAsmConstraint function should only accept MVT value types. 2013-06-22 18:37:38 +00:00
MipsISelLowering.h The getRegForInlineAsmConstraint function should only accept MVT value types. 2013-06-22 18:37:38 +00:00
MipsJITInfo.cpp
MipsJITInfo.h
MipsLongBranch.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
MipsMachineFunction.cpp
MipsMachineFunction.h
MipsMCInstLower.cpp
MipsMCInstLower.h
MipsModuleISelDAGToDAG.cpp
MipsModuleISelDAGToDAG.h
MipsOptimizeMathLibCalls.cpp [mips] Add an IR transformation pass that optimizes calls to sqrt. 2013-06-11 22:21:44 +00:00
MipsOs16.cpp
MipsOs16.h
MipsRegisterInfo.cpp
MipsRegisterInfo.h
MipsRegisterInfo.td This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. 2013-06-24 10:05:34 +00:00
MipsRelocations.h
MipsSchedule.td
MipsSEFrameLowering.cpp Use pointers to the MCAsmInfo and MCRegInfo. 2013-06-18 07:20:20 +00:00
MipsSEFrameLowering.h
MipsSEInstrInfo.cpp [mips] Use function TargetInstrInfo::getRegClass. 2013-06-11 18:48:16 +00:00
MipsSEInstrInfo.h [mips] Use function TargetInstrInfo::getRegClass. 2013-06-11 18:48:16 +00:00
MipsSEISelDAGToDAG.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 21:36:55 +00:00
MipsSEISelDAGToDAG.h Track IR ordering of SelectionDAG nodes 2/4. 2013-05-25 02:42:55 +00:00
MipsSEISelLowering.cpp Track IR ordering of SelectionDAG nodes 2/4. 2013-05-25 02:42:55 +00:00
MipsSEISelLowering.h
MipsSelectionDAGInfo.cpp
MipsSelectionDAGInfo.h
MipsSERegisterInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
MipsSERegisterInfo.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 07:04:14 +00:00
MipsSubtarget.cpp
MipsSubtarget.h
MipsTargetMachine.cpp [mips] Add an IR transformation pass that optimizes calls to sqrt. 2013-06-11 22:21:44 +00:00
MipsTargetMachine.h
MipsTargetObjectFile.cpp
MipsTargetObjectFile.h