mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-31 12:30:06 +00:00
a46a100945
Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132690 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.7 KiB
C++
82 lines
2.7 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements an allocation order for virtual registers.
|
|
//
|
|
// The preferred allocation order for a virtual register depends on allocation
|
|
// hints and target hooks. The AllocationOrder class encapsulates all of that.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "AllocationOrder.h"
|
|
#include "RegisterClassInfo.h"
|
|
#include "VirtRegMap.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
|
|
using namespace llvm;
|
|
|
|
// Compare VirtRegMap::getRegAllocPref().
|
|
AllocationOrder::AllocationOrder(unsigned VirtReg,
|
|
const VirtRegMap &VRM,
|
|
const RegisterClassInfo &RegClassInfo)
|
|
: Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
|
|
const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
|
|
std::pair<unsigned, unsigned> HintPair =
|
|
VRM.getRegInfo().getRegAllocationHint(VirtReg);
|
|
|
|
// HintPair.second is a register, phys or virt.
|
|
Hint = HintPair.second;
|
|
|
|
// Translate to physreg, or 0 if not assigned yet.
|
|
if (TargetRegisterInfo::isVirtualRegister(Hint))
|
|
Hint = VRM.getPhys(Hint);
|
|
|
|
// The first hint pair component indicates a target-specific hint.
|
|
if (HintPair.first) {
|
|
const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
|
|
// The remaining allocation order may depend on the hint.
|
|
const unsigned *B, *E;
|
|
tie(B, E) = TRI.getAllocationOrder(RC, HintPair.first, Hint,
|
|
VRM.getMachineFunction());
|
|
|
|
// Empty allocation order?
|
|
if (B == E)
|
|
return;
|
|
|
|
// Copy the allocation order with reserved registers removed.
|
|
OwnedBegin = true;
|
|
unsigned *P = new unsigned[E - B];
|
|
Begin = P;
|
|
for (; B != E; ++B)
|
|
if (!RCI.isReserved(*B))
|
|
*P++ = *B;
|
|
End = P;
|
|
|
|
// Target-dependent hints require resolution.
|
|
Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint,
|
|
VRM.getMachineFunction());
|
|
} else {
|
|
// If there is no hint or just a normal hint, use the cached allocation
|
|
// order from RegisterClassInfo.
|
|
ArrayRef<unsigned> O = RCI.getOrder(RC);
|
|
Begin = O.begin();
|
|
End = O.end();
|
|
}
|
|
|
|
// The hint must be a valid physreg for allocation.
|
|
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
|
|
!RC->contains(Hint) || RCI.isReserved(Hint)))
|
|
Hint = 0;
|
|
}
|
|
|
|
AllocationOrder::~AllocationOrder() {
|
|
if (OwnedBegin)
|
|
delete [] Begin;
|
|
}
|