mirror of
https://github.com/c64scene-ar/llvm-6502.git
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860cabe1e6
VGPRs are spilled to LDS. This still needs more testing, but
we need to at least enable it at -O0, because the fast register
allocator spills all registers that are live at the end of blocks
and without this some future commits will break the
flat-address-space.ll test.
v2: Only calculate thread id once
v3: Move insertion of spill instructions to
SIRegisterInfo::eliminateFrameIndex()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218348 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.5 KiB
C++
77 lines
2.5 KiB
C++
//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "SIMachineFunctionInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#define MAX_LANES 64
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using namespace llvm;
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// Pin the vtable to this file.
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void SIMachineFunctionInfo::anchor() {}
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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TIDReg(AMDGPU::NoRegister),
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PSInputAddr(0),
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NumUserSGPRs(0),
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LDSWaveSpillSize(0) { }
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SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
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MachineFunction *MF,
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unsigned FrameIndex,
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unsigned SubIdx) {
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const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo*>(
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MF->getTarget().getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
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MachineRegisterInfo &MRI = MF->getRegInfo();
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int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
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Offset += SubIdx * 4;
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unsigned LaneVGPRIdx = Offset / (64 * 4);
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unsigned Lane = (Offset / 4) % 64;
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struct SpilledReg Spill;
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if (!LaneVGPRs.count(LaneVGPRIdx)) {
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unsigned LaneVGPR = TRI->findUnusedVGPR(MRI);
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LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
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MRI.setPhysRegUsed(LaneVGPR);
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
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BI != BE; ++BI) {
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BI->addLiveIn(LaneVGPR);
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}
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}
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Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
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Spill.Lane = Lane;
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return Spill;
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}
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unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
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const MachineFunction &MF) const {
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const AMDGPUSubtarget &ST = MF.getTarget().getSubtarget<AMDGPUSubtarget>();
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// FIXME: We should get this information from kernel attributes if it
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// is available.
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return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();
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}
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