mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-03 02:30:00 +00:00
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176105 91177308-0d34-0410-b5e6-96231b3b80d8
611 lines
19 KiB
C++
611 lines
19 KiB
C++
//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Custom DAG lowering for SI
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//
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//===----------------------------------------------------------------------===//
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#include "SIISelLowering.h"
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#include "AMDIL.h"
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#include "AMDILIntrinsicInfo.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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using namespace llvm;
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SITargetLowering::SITargetLowering(TargetMachine &TM) :
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AMDGPUTargetLowering(TM),
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TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
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TRI(TM.getRegisterInfo()) {
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addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
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addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
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addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
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addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
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addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
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computeRegisterProperties();
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setOperationAction(ISD::ADD, MVT::i64, Legal);
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setOperationAction(ISD::ADD, MVT::i32, Legal);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// We need to custom lower loads from the USER_SGPR address space, so we can
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// add the SGPRs as livein registers.
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::LOAD, MVT::i64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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}
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MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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MachineInstr * MI, MachineBasicBlock * BB) const {
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MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
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MachineBasicBlock::iterator I = MI;
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switch (MI->getOpcode()) {
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default:
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return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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case AMDGPU::BRANCH: return BB;
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case AMDGPU::SHADER_TYPE:
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BB->getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType =
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MI->getOperand(0).getImm();
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MI->eraseFromParent();
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break;
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case AMDGPU::SI_INTERP:
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LowerSI_INTERP(MI, *BB, I, MRI);
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break;
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case AMDGPU::SI_WQM:
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LowerSI_WQM(MI, *BB, I, MRI);
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break;
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}
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return BB;
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}
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void SITargetLowering::LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC);
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MI->eraseFromParent();
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}
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void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
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unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
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MachineOperand dst = MI->getOperand(0);
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MachineOperand iReg = MI->getOperand(1);
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MachineOperand jReg = MI->getOperand(2);
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MachineOperand attr_chan = MI->getOperand(3);
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MachineOperand attr = MI->getOperand(4);
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MachineOperand params = MI->getOperand(5);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
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.addOperand(params);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
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.addOperand(iReg)
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.addOperand(attr_chan)
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.addOperand(attr)
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.addReg(M0);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
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.addOperand(dst)
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.addReg(tmp)
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.addOperand(jReg)
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.addOperand(attr_chan)
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.addOperand(attr)
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.addReg(M0);
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MI->eraseFromParent();
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}
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EVT SITargetLowering::getSetCCResultType(EVT VT) const {
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return MVT::i1;
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}
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//===----------------------------------------------------------------------===//
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// Custom DAG Lowering Operations
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//===----------------------------------------------------------------------===//
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SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::LOAD: return LowerLOAD(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntrinsicID =
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cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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EVT VT = Op.getValueType();
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switch (IntrinsicID) {
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case AMDGPUIntrinsic::SI_vs_load_buffer_index:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR0, VT);
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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}
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break;
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}
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}
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return SDValue();
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}
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/// \brief Helper function for LowerBRCOND
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static SDNode *findUser(SDValue Value, unsigned Opcode) {
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SDNode *Parent = Value.getNode();
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for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
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I != E; ++I) {
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if (I.getUse().get() != Value)
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continue;
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if (I->getOpcode() == Opcode)
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return *I;
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}
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return 0;
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}
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/// This transforms the control flow intrinsics to get the branch destination as
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/// last parameter, also switches branch target with BR if the need arise
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SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
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SelectionDAG &DAG) const {
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DebugLoc DL = BRCOND.getDebugLoc();
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SDNode *Intr = BRCOND.getOperand(1).getNode();
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SDValue Target = BRCOND.getOperand(2);
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SDNode *BR = 0;
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if (Intr->getOpcode() == ISD::SETCC) {
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// As long as we negate the condition everything is fine
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SDNode *SetCC = Intr;
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assert(SetCC->getConstantOperandVal(1) == 1);
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assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
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ISD::SETNE);
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Intr = SetCC->getOperand(0).getNode();
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} else {
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// Get the target from BR if we don't negate the condition
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BR = findUser(BRCOND, ISD::BR);
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Target = BR->getOperand(1);
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}
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assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
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// Build the result and
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SmallVector<EVT, 4> Res;
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for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
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Res.push_back(Intr->getValueType(i));
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// operands of the new intrinsic call
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SmallVector<SDValue, 4> Ops;
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Ops.push_back(BRCOND.getOperand(0));
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for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
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Ops.push_back(Intr->getOperand(i));
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Ops.push_back(Target);
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// build the new intrinsic call
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SDNode *Result = DAG.getNode(
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Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
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DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode();
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if (BR) {
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// Give the branch instruction our target
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SDValue Ops[] = {
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BR->getOperand(0),
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BRCOND.getOperand(2)
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};
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DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2);
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}
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SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
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// Copy the intrinsic results to registers
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for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
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SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
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if (!CopyToReg)
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continue;
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Chain = DAG.getCopyToReg(
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Chain, DL,
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CopyToReg->getOperand(1),
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SDValue(Result, i - 1),
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SDValue());
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DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
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}
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// Remove the old intrinsic from the chain
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DAG.ReplaceAllUsesOfValueWith(
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SDValue(Intr, Intr->getNumValues() - 1),
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Intr->getOperand(0));
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return Chain;
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}
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SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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LoadSDNode *Ptr = dyn_cast<LoadSDNode>(Op);
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assert(Ptr);
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unsigned AddrSpace = Ptr->getPointerInfo().getAddrSpace();
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// We only need to lower USER_SGPR address space loads
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if (AddrSpace != AMDGPUAS::USER_SGPR_ADDRESS) {
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return SDValue();
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}
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// Loads from the USER_SGPR address space can only have constant value
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// pointers.
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ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
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assert(BasePtr);
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unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
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const TargetRegisterClass * dstClass;
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switch (TypeDwordWidth) {
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default:
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assert(!"USER_SGPR value size not implemented");
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return SDValue();
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case 1:
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dstClass = &AMDGPU::SReg_32RegClass;
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break;
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case 2:
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dstClass = &AMDGPU::SReg_64RegClass;
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break;
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}
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uint64_t Index = BasePtr->getZExtValue();
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assert(Index % TypeDwordWidth == 0 && "USER_SGPR not properly aligned");
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unsigned SGPRIndex = Index / TypeDwordWidth;
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unsigned Reg = dstClass->getRegister(SGPRIndex);
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DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
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VT));
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return SDValue();
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}
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SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue True = Op.getOperand(2);
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SDValue False = Op.getOperand(3);
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SDValue CC = Op.getOperand(4);
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EVT VT = Op.getValueType();
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DebugLoc DL = Op.getDebugLoc();
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// Possible Min/Max pattern
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SDValue MinMax = LowerMinMax(Op, DAG);
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if (MinMax.getNode()) {
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return MinMax;
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}
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SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
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return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
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}
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//===----------------------------------------------------------------------===//
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// Custom DAG optimizations
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//===----------------------------------------------------------------------===//
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SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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DebugLoc DL = N->getDebugLoc();
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EVT VT = N->getValueType(0);
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switch (N->getOpcode()) {
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default: break;
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case ISD::SELECT_CC: {
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N->dump();
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ConstantSDNode *True, *False;
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// i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
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if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
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&& (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
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&& True->isAllOnesValue()
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&& False->isNullValue()
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&& VT == MVT::i1) {
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return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
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N->getOperand(1), N->getOperand(4));
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}
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break;
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}
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case ISD::SETCC: {
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SDValue Arg0 = N->getOperand(0);
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SDValue Arg1 = N->getOperand(1);
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SDValue CC = N->getOperand(2);
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ConstantSDNode * C = NULL;
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ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
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// i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
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if (VT == MVT::i1
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&& Arg0.getOpcode() == ISD::SIGN_EXTEND
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&& Arg0.getOperand(0).getValueType() == MVT::i1
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&& (C = dyn_cast<ConstantSDNode>(Arg1))
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&& C->isNullValue()
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&& CCOp == ISD::SETNE) {
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return SimplifySetCC(VT, Arg0.getOperand(0),
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DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
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}
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break;
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}
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}
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return SDValue();
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}
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/// \brief Test if RegClass is one of the VSrc classes
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static bool isVSrc(unsigned RegClass) {
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return AMDGPU::VSrc_32RegClassID == RegClass ||
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AMDGPU::VSrc_64RegClassID == RegClass;
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}
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/// \brief Test if RegClass is one of the SSrc classes
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static bool isSSrc(unsigned RegClass) {
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return AMDGPU::SSrc_32RegClassID == RegClass ||
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AMDGPU::SSrc_64RegClassID == RegClass;
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}
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/// \brief Analyze the possible immediate value Op
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///
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/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
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/// and the immediate value if it's a literal immediate
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int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
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union {
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int32_t I;
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float F;
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} Imm;
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if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N))
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Imm.I = Node->getSExtValue();
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else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
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Imm.F = Node->getValueAPF().convertToFloat();
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else
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return -1; // It isn't an immediate
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if ((Imm.I >= -16 && Imm.I <= 64) ||
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Imm.F == 0.5f || Imm.F == -0.5f ||
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Imm.F == 1.0f || Imm.F == -1.0f ||
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Imm.F == 2.0f || Imm.F == -2.0f ||
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Imm.F == 4.0f || Imm.F == -4.0f)
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return 0; // It's an inline immediate
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return Imm.I; // It's a literal immediate
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}
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/// \brief Try to fold an immediate directly into an instruction
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bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
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bool &ScalarSlotUsed) const {
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MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
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if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
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return false;
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const SDValue &Op = Mov->getOperand(0);
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int32_t Value = analyzeImmediate(Op.getNode());
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if (Value == -1) {
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// Not an immediate at all
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return false;
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} else if (Value == 0) {
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// Inline immediates can always be fold
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Operand = Op;
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return true;
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} else if (Value == Immediate) {
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// Already fold literal immediate
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Operand = Op;
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return true;
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} else if (!ScalarSlotUsed && !Immediate) {
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// Fold this literal immediate
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ScalarSlotUsed = true;
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Immediate = Value;
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Operand = Op;
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return true;
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}
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return false;
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}
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/// \brief Does "Op" fit into register class "RegClass" ?
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bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
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unsigned RegClass) const {
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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SDNode *Node = Op.getNode();
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int OpClass;
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if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
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const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
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OpClass = Desc.OpInfo[Op.getResNo()].RegClass;
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} else if (Node->getOpcode() == ISD::CopyFromReg) {
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RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());
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OpClass = MRI.getRegClass(Reg->getReg())->getID();
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} else
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return false;
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if (OpClass == -1)
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return false;
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return TRI->getRegClass(RegClass)->hasSubClassEq(TRI->getRegClass(OpClass));
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}
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/// \brief Make sure that we don't exeed the number of allowed scalars
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void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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unsigned RegClass,
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bool &ScalarSlotUsed) const {
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// First map the operands register class to a destination class
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if (RegClass == AMDGPU::VSrc_32RegClassID)
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RegClass = AMDGPU::VReg_32RegClassID;
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else if (RegClass == AMDGPU::VSrc_64RegClassID)
|
|
RegClass = AMDGPU::VReg_64RegClassID;
|
|
else
|
|
return;
|
|
|
|
// Nothing todo if they fit naturaly
|
|
if (fitsRegClass(DAG, Operand, RegClass))
|
|
return;
|
|
|
|
// If the scalar slot isn't used yet use it now
|
|
if (!ScalarSlotUsed) {
|
|
ScalarSlotUsed = true;
|
|
return;
|
|
}
|
|
|
|
// This is a conservative aproach, it is possible that we can't determine
|
|
// the correct register class and copy too often, but better save than sorry.
|
|
SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
|
|
SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DebugLoc(),
|
|
Operand.getValueType(), Operand, RC);
|
|
Operand = SDValue(Node, 0);
|
|
}
|
|
|
|
SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
|
|
SelectionDAG &DAG) const {
|
|
|
|
// Original encoding (either e32 or e64)
|
|
int Opcode = Node->getMachineOpcode();
|
|
const MCInstrDesc *Desc = &TII->get(Opcode);
|
|
|
|
unsigned NumDefs = Desc->getNumDefs();
|
|
unsigned NumOps = Desc->getNumOperands();
|
|
|
|
// e64 version if available, -1 otherwise
|
|
int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
|
|
const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
|
|
|
|
assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
|
|
assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
|
|
|
|
int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
|
|
bool HaveVSrc = false, HaveSSrc = false;
|
|
|
|
// First figure out what we alread have in this instruction
|
|
for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
|
|
i != e && Op < NumOps; ++i, ++Op) {
|
|
|
|
unsigned RegClass = Desc->OpInfo[Op].RegClass;
|
|
if (isVSrc(RegClass))
|
|
HaveVSrc = true;
|
|
else if (isSSrc(RegClass))
|
|
HaveSSrc = true;
|
|
else
|
|
continue;
|
|
|
|
int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
|
|
if (Imm != -1 && Imm != 0) {
|
|
// Literal immediate
|
|
Immediate = Imm;
|
|
}
|
|
}
|
|
|
|
// If we neither have VSrc nor SSrc it makes no sense to continue
|
|
if (!HaveVSrc && !HaveSSrc)
|
|
return Node;
|
|
|
|
// No scalar allowed when we have both VSrc and SSrc
|
|
bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
|
|
|
|
// Second go over the operands and try to fold them
|
|
std::vector<SDValue> Ops;
|
|
bool Promote2e64 = false;
|
|
for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
|
|
i != e && Op < NumOps; ++i, ++Op) {
|
|
|
|
const SDValue &Operand = Node->getOperand(i);
|
|
Ops.push_back(Operand);
|
|
|
|
// Already folded immediate ?
|
|
if (isa<ConstantSDNode>(Operand.getNode()) ||
|
|
isa<ConstantFPSDNode>(Operand.getNode()))
|
|
continue;
|
|
|
|
// Is this a VSrc or SSrc operand ?
|
|
unsigned RegClass = Desc->OpInfo[Op].RegClass;
|
|
if (!isVSrc(RegClass) && !isSSrc(RegClass)) {
|
|
|
|
if (i == 1 && Desc->isCommutable() &&
|
|
fitsRegClass(DAG, Ops[0], RegClass) &&
|
|
foldImm(Ops[1], Immediate, ScalarSlotUsed)) {
|
|
|
|
assert(isVSrc(Desc->OpInfo[NumDefs].RegClass) ||
|
|
isSSrc(Desc->OpInfo[NumDefs].RegClass));
|
|
|
|
// Swap commutable operands
|
|
SDValue Tmp = Ops[1];
|
|
Ops[1] = Ops[0];
|
|
Ops[0] = Tmp;
|
|
|
|
} else if (DescE64 && !Immediate) {
|
|
// Test if it makes sense to switch to e64 encoding
|
|
|
|
RegClass = DescE64->OpInfo[Op].RegClass;
|
|
int32_t TmpImm = -1;
|
|
if ((isVSrc(RegClass) || isSSrc(RegClass)) &&
|
|
foldImm(Ops[i], TmpImm, ScalarSlotUsed)) {
|
|
|
|
Immediate = -1;
|
|
Promote2e64 = true;
|
|
Desc = DescE64;
|
|
DescE64 = 0;
|
|
}
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// Try to fold the immediates
|
|
if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
|
|
// Folding didn't worked, make sure we don't hit the SReg limit
|
|
ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
|
|
}
|
|
}
|
|
|
|
if (Promote2e64) {
|
|
// Add the modifier flags while promoting
|
|
for (unsigned i = 0; i < 4; ++i)
|
|
Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
|
|
}
|
|
|
|
// Add optional chain and glue
|
|
for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
|
|
Ops.push_back(Node->getOperand(i));
|
|
|
|
// Either create a complete new or update the current instruction
|
|
if (Promote2e64)
|
|
return DAG.getMachineNode(OpcodeE64, Node->getDebugLoc(),
|
|
Node->getVTList(), Ops.data(), Ops.size());
|
|
else
|
|
return DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
|
|
}
|