mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-03 02:30:00 +00:00
6fd49bc89a
Prevent producing real strange tablegen code by using
proper register sizes, alignments and hierarchy.
Also cleanup the unused definitions and add some comments.
v2: add SGPR 512 bit registers, stop registers from wrapping around,
fix SGPR alignment
This is a candidate for the mesa-stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176098 91177308-0d34-0410-b5e6-96231b3b80d8
228 lines
9.5 KiB
TableGen
228 lines
9.5 KiB
TableGen
//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the SI registers
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//===----------------------------------------------------------------------===//
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class SIReg <string n, bits<16> encoding = 0> : Register<n> {
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let Namespace = "AMDGPU";
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let HWEncoding = encoding;
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}
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// Special Registers
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def VCC : SIReg<"VCC", 106>;
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def EXEC : SIReg<"EXEC", 126>;
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def SCC : SIReg<"SCC", 253>;
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def M0 : SIReg <"M0", 124>;
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// SGPR registers
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foreach Index = 0-101 in {
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def SGPR#Index : SIReg <"SGPR"#Index, Index>;
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}
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// VGPR registers
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foreach Index = 0-255 in {
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def VGPR#Index : SIReg <"VGPR"#Index, Index> {
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let HWEncoding{8} = 1;
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}
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}
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// virtual Interpolation registers
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def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">;
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def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">;
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def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">;
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def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">;
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def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">;
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def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">;
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def PERSP_I_W : SIReg <"PERSP_I_W">;
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def PERSP_J_W : SIReg <"PERSP_J_W">;
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def PERSP_1_W : SIReg <"PERSP_1_W">;
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def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">;
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def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">;
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def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">;
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def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">;
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def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">;
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def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">;
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def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">;
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def POS_X_FLOAT : SIReg <"POS_X_FLOAT">;
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def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">;
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def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">;
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def POS_W_FLOAT : SIReg <"POS_W_FLOAT">;
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def FRONT_FACE : SIReg <"FRONT_FACE">;
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def ANCILLARY : SIReg <"ANCILLARY">;
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def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">;
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def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
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//===----------------------------------------------------------------------===//
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// Groupings using register classes and tuples
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//===----------------------------------------------------------------------===//
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// SGPR 32-bit registers
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def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add (sequence "SGPR%u", 0, 101))>;
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// SGPR 64-bit registers
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def SGPR_64 : RegisterTuples<[sub0, sub1],
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[(add (decimate (trunc SGPR_32, 101), 2)),
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(add (decimate (shl SGPR_32, 1), 2))]>;
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// SGPR 128-bit registers
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def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
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[(add (decimate (trunc SGPR_32, 99), 4)),
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(add (decimate (shl SGPR_32, 1), 4)),
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(add (decimate (shl SGPR_32, 2), 4)),
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(add (decimate (shl SGPR_32, 3), 4))]>;
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// SGPR 256-bit registers
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def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
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[(add (decimate (trunc SGPR_32, 95), 4)),
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(add (decimate (shl SGPR_32, 1), 4)),
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(add (decimate (shl SGPR_32, 2), 4)),
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(add (decimate (shl SGPR_32, 3), 4)),
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(add (decimate (shl SGPR_32, 4), 4)),
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(add (decimate (shl SGPR_32, 5), 4)),
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(add (decimate (shl SGPR_32, 6), 4)),
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(add (decimate (shl SGPR_32, 7), 4))]>;
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// SGPR 512-bit registers
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def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
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[(add (decimate (trunc SGPR_32, 87), 4)),
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(add (decimate (shl SGPR_32, 1), 4)),
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(add (decimate (shl SGPR_32, 2), 4)),
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(add (decimate (shl SGPR_32, 3), 4)),
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(add (decimate (shl SGPR_32, 4), 4)),
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(add (decimate (shl SGPR_32, 5), 4)),
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(add (decimate (shl SGPR_32, 6), 4)),
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(add (decimate (shl SGPR_32, 7), 4)),
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(add (decimate (shl SGPR_32, 8), 4)),
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(add (decimate (shl SGPR_32, 9), 4)),
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(add (decimate (shl SGPR_32, 10), 4)),
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(add (decimate (shl SGPR_32, 11), 4)),
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(add (decimate (shl SGPR_32, 12), 4)),
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(add (decimate (shl SGPR_32, 13), 4)),
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(add (decimate (shl SGPR_32, 14), 4)),
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(add (decimate (shl SGPR_32, 15), 4))]>;
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// VGPR 32-bit registers
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def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add (sequence "VGPR%u", 0, 255))>;
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// VGPR 64-bit registers
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def VGPR_64 : RegisterTuples<[sub0, sub1],
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[(add (trunc VGPR_32, 255)),
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(add (shl VGPR_32, 1))]>;
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// VGPR 128-bit registers
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def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
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[(add (trunc VGPR_32, 253)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2)),
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(add (shl VGPR_32, 3))]>;
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// VGPR 256-bit registers
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def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
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[(add (trunc VGPR_32, 249)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2)),
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(add (shl VGPR_32, 3)),
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(add (shl VGPR_32, 4)),
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(add (shl VGPR_32, 5)),
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(add (shl VGPR_32, 6)),
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(add (shl VGPR_32, 7))]>;
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// VGPR 512-bit registers
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def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
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[(add (trunc VGPR_32, 241)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2)),
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(add (shl VGPR_32, 3)),
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(add (shl VGPR_32, 4)),
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(add (shl VGPR_32, 5)),
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(add (shl VGPR_32, 6)),
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(add (shl VGPR_32, 7)),
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(add (shl VGPR_32, 8)),
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(add (shl VGPR_32, 9)),
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(add (shl VGPR_32, 10)),
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(add (shl VGPR_32, 11)),
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(add (shl VGPR_32, 12)),
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(add (shl VGPR_32, 13)),
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(add (shl VGPR_32, 14)),
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(add (shl VGPR_32, 15))]>;
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//===----------------------------------------------------------------------===//
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// Register classes used as source and destination
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//===----------------------------------------------------------------------===//
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// Special register classes for predicates and the M0 register
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def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
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def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
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def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
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def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
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// Register class for all scalar registers (SGPRs + Special Registers)
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def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add SGPR_32, M0Reg)
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>;
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def SReg_64 : RegisterClass<"AMDGPU", [i64, i1], 64,
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(add SGPR_64, VCCReg, EXECReg)
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>;
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def SReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add SGPR_128)>;
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def SReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add SGPR_256)>;
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def SReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add SGPR_512)>;
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// Register class for all vector registers (VGPRs + Interploation Registers)
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def VReg_32 : RegisterClass<"AMDGPU", [f32, i32, v1i32], 32, (add VGPR_32)>;
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def VReg_64 : RegisterClass<"AMDGPU", [i64, v2i32], 64, (add VGPR_64)>;
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def VReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add VGPR_128)>;
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def VReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add VGPR_256)>;
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def VReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add VGPR_512)>;
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//===----------------------------------------------------------------------===//
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// [SV]Src_* register classes, can have either an immediate or an register
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//===----------------------------------------------------------------------===//
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def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
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def SSrc_64 : RegisterClass<"AMDGPU", [i64, i1], 64, (add SReg_64)>;
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def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
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(add VReg_32, SReg_32,
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PERSP_SAMPLE_I, PERSP_SAMPLE_J,
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PERSP_CENTER_I, PERSP_CENTER_J,
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PERSP_CENTROID_I, PERSP_CENTROID_J,
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PERSP_I_W, PERSP_J_W, PERSP_1_W,
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LINEAR_SAMPLE_I, LINEAR_SAMPLE_J,
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LINEAR_CENTER_I, LINEAR_CENTER_J,
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LINEAR_CENTROID_I, LINEAR_CENTROID_J,
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LINE_STIPPLE_TEX_COORD,
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POS_X_FLOAT,
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POS_Y_FLOAT,
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POS_Z_FLOAT,
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POS_W_FLOAT,
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FRONT_FACE,
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ANCILLARY,
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SAMPLE_COVERAGE,
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POS_FIXED_PT
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)
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>;
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def VSrc_64 : RegisterClass<"AMDGPU", [i64], 64, (add VReg_64, SReg_64)>;
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