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https://github.com/c64scene-ar/llvm-6502.git
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5ea7215050
LowerVSELECT will, if possible, generate a X86ISD::BLENDI DAG node if the condition is constant and we can emit that instruction, given the subtarget. This is not enough for all cases. An additional SELECTCombine optimization will be committed. Fixed tests that were expecting variable blends but where a blend+imm can be generated. Added test where we can't emit blend+immediate. Added avx2 blend+imm tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209043 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
2.7 KiB
LLVM
91 lines
2.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
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;CHECK-LABEL: vsel_float:
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;CHECK: blendps
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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;CHECK-LABEL: vsel_4xi8:
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;CHECK: blendps
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;CHECK: ret
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define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i8> %v1, <4 x i8> %v2
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ret <4 x i8> %vsel
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}
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;CHECK-LABEL: vsel_4xi16:
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;CHECK: blendps
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;CHECK: ret
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define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i16> %v1, <4 x i16> %v2
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ret <4 x i16> %vsel
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}
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;CHECK-LABEL: vsel_i32:
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;CHECK: blendps
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;CHECK: ret
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define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> %v1, <4 x i32> %v2
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ret <4 x i32> %vsel
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}
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;CHECK-LABEL: vsel_double:
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;CHECK: movsd
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;CHECK: ret
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define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %v1, <4 x double> %v2
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ret <4 x double> %vsel
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}
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;CHECK-LABEL: vsel_i64:
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;CHECK: movsd
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;CHECK: ret
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define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v1, <4 x i64> %v2
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ret <4 x i64> %vsel
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}
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;CHECK-LABEL: vsel_i8:
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;CHECK: pblendvb
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;CHECK: ret
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define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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%vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
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ret <16 x i8> %vsel
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}
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;; TEST blend + compares
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; CHECK: A
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define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
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; CHECK: cmplepd
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; CHECK: blendvpd
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%max_is_x = fcmp oge <2 x double> %x, %y
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%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %max
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}
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; CHECK: B
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define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
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; CHECK: cmpnlepd
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; CHECK: blendvpd
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%min_is_x = fcmp ult <2 x double> %x, %y
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %min
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}
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; CHECK: float_crash
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define void @float_crash() nounwind {
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entry:
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%merge205vector_func.i = select <4 x i1> undef, <4 x double> undef, <4 x double> undef
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%extract214vector_func.i = extractelement <4 x double> %merge205vector_func.i, i32 0
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store double %extract214vector_func.i, double addrspace(1)* undef, align 8
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ret void
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}
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