Mihai Popa 62d77858be s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-30 09:00:12 +00:00
..
AArch64	AArch64: implement ETMv4 trace system registers.	2013-04-03 12:31:29 +00:00
ARM	s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.	2013-04-30 09:00:12 +00:00
MBlaze
Mips	[mips] DSP-ASE move from HI/LO register instructions.	2013-04-18 00:52:44 +00:00
X86	Add CLAC/STAC instruction encoding/decoding support	2013-04-11 04:52:28 +00:00
XCore	Use object file specific section type for initial text section	2013-04-14 21:18:36 +00:00