Ulrich Weigand e4b2165648 [PowerPC] Fix FrameIndex handling in SelectAddressRegImm ... The PPCTargetLowering::SelectAddressRegImm routine needs to handle FrameIndex nodes in a special manner, by tranlating them into a TargetFrameIndex node. This was done in most cases, but seems to have been neglected in one path: when the input tree has an OR of the FrameIndex with an immediate. This can happen if the FrameIndex can be proven to be sufficiently aligned that an OR of that immediate is equivalent to an ADD. The missing handling of FrameIndex in that case caused the SelectionDAG instruction selection to miss opportunities to merge the OR back into the FrameIndex node, leading to superfluous addi/ori instructions in the final assembler output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213482 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-20 22:26:40 +00:00
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AArch64	AArch64: implement efficient f16 bitcasts	2014-07-18 13:07:05 +00:00
ARM	ARM: correct WoA __builtin_alloca handling on O0	2014-07-19 01:29:51 +00:00
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NVPTX	Add tests for atomic adds on floats.	2014-07-18 20:11:26 +00:00
PowerPC	[PowerPC] Fix FrameIndex handling in SelectAddressRegImm	2014-07-20 22:26:40 +00:00
R600	R600: Add missing test for concat_vectors	2014-07-20 07:13:17 +00:00
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X86	[x86] Fix wrong shuffle mask in test 'combine-vec-shuffle-3.ll'. No functional change.	2014-07-19 07:52:58 +00:00
XCore