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https://github.com/c64scene-ar/llvm-6502.git
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8b2b8a1835
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
1.8 KiB
LLVM
79 lines
1.8 KiB
LLVM
; Test 64-bit GPR loads.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check LG with no displacement.
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define i64 @f1(i64 *%src) {
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; CHECK-LABEL: f1:
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; CHECK: lg %r2, 0(%r2)
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; CHECK: br %r14
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%val = load i64 *%src
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ret i64 %val
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}
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; Check the high end of the aligned LG range.
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define i64 @f2(i64 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: lg %r2, 524280(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65535
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%val = load i64 *%ptr
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ret i64 %val
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f3(i64 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: lg %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65536
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%val = load i64 *%ptr
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ret i64 %val
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}
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; Check the high end of the negative aligned LG range.
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define i64 @f4(i64 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: lg %r2, -8(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -1
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%val = load i64 *%ptr
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ret i64 %val
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}
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; Check the low end of the LG range.
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define i64 @f5(i64 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: lg %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65536
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%val = load i64 *%ptr
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ret i64 %val
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f6(i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r2, -524296
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; CHECK: lg %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65537
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%val = load i64 *%ptr
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ret i64 %val
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}
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; Check that LG allows an index.
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define i64 @f7(i64 %src, i64 %index) {
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; CHECK-LABEL: f7:
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; CHECK: lg %r2, 524287({{%r3,%r2|%r2,%r3}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%val = load i64 *%ptr
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ret i64 %val
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}
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