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PowerPC has a conditional branch to the link register (return) instruction: BCLR. This should be used any time when we'd otherwise have a conditional branch to a return. This adds a small pass, PPCEarlyReturn, which runs just prior to the branch selection pass (and, importantly, after block placement) to generate these conditional returns when possible. It will also eliminate unconditional branches to returns (these happen rarely; most of the time these have already been tail duplicated by the time PPCEarlyReturn is invoked). This is a nice optimization for small functions that do not maintain a stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179026 91177308-0d34-0410-b5e6-96231b3b80d8
154 lines
5.0 KiB
C++
154 lines
5.0 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCTargetMachine.h"
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#include "PPC.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::
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opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
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cl::desc("Disable CTR loops for PPC"));
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
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RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
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}
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PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64Bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, is64Bit),
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DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
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FrameLowering(Subtarget), JITInfo(*this, is64Bit),
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TLInfo(*this), TSInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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// The binutils for the BG/P are too old for CFI.
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if (Subtarget.isBGP())
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setMCUseCFI(false);
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}
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void PPC32TargetMachine::anchor() { }
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PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void PPC64TargetMachine::anchor() { }
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PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// PPC Code Generator Pass Configuration Options.
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class PPCPassConfig : public TargetPassConfig {
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public:
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PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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PPCTargetMachine &getPPCTargetMachine() const {
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return getTM<PPCTargetMachine>();
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}
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const PPCSubtarget &getPPCSubtarget() const {
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return *getPPCTargetMachine().getSubtargetImpl();
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}
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virtual bool addPreRegAlloc();
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virtual bool addILPOpts();
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new PPCPassConfig(this, PM);
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}
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bool PPCPassConfig::addPreRegAlloc() {
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCCTRLoops());
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return false;
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}
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bool PPCPassConfig::addILPOpts() {
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if (getPPCSubtarget().hasISEL()) {
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addPass(&EarlyIfConverterID);
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return true;
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}
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return false;
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}
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bool PPCPassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createPPCISelDag(getPPCTargetMachine()));
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return false;
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}
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bool PPCPassConfig::addPreEmitPass() {
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createPPCEarlyReturnPass());
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// Must run branch selection immediately preceding the asm printer.
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addPass(createPPCBranchSelectionPass());
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return false;
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}
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bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
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// writing?
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Subtarget.SetJITMode();
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCJITCodeEmitterPass(*this, JCE));
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return false;
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}
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void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our PPC pass. This
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// allows the PPC pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
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PM.add(createPPCTargetTransformInfoPass(this));
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}
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