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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97680 91177308-0d34-0410-b5e6-96231b3b80d8
457 lines
19 KiB
C++
457 lines
19 KiB
C++
//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineInstr class, which is the
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// basic representation for all target dependent machine instructions used by
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// the back end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/ADT/ilist.h"
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#include "llvm/ADT/ilist_node.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/Target/TargetInstrDesc.h"
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#include "llvm/Target/TargetOpcodes.h"
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#include "llvm/Support/DebugLoc.h"
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#include <vector>
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namespace llvm {
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class AliasAnalysis;
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class TargetInstrDesc;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class MachineFunction;
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class MachineMemOperand;
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//===----------------------------------------------------------------------===//
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/// MachineInstr - Representation of each machine instruction.
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///
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class MachineInstr : public ilist_node<MachineInstr> {
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public:
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typedef MachineMemOperand **mmo_iterator;
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/// Flags to specify different kinds of comments to output in
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/// assembly code. These flags carry semantic information not
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/// otherwise easily derivable from the IR text.
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///
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enum CommentFlag {
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ReloadReuse = 0x1
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};
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private:
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const TargetInstrDesc *TID; // Instruction descriptor.
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unsigned short NumImplicitOps; // Number of implicit operands (which
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// are determined at construction time).
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unsigned short AsmPrinterFlags; // Various bits of information used by
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// the AsmPrinter to emit helpful
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// comments. This is *not* semantic
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// information. Do not use this for
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// anything other than to convey comment
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// information to AsmPrinter.
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std::vector<MachineOperand> Operands; // the operands
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mmo_iterator MemRefs; // information on memory references
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mmo_iterator MemRefsEnd;
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MachineBasicBlock *Parent; // Pointer to the owning basic block.
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DebugLoc debugLoc; // Source line information.
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// OperandComplete - Return true if it's illegal to add a new operand
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bool OperandsComplete() const;
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MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
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void operator=(const MachineInstr&); // DO NOT IMPLEMENT
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// Intrusive list support
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friend struct ilist_traits<MachineInstr>;
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friend struct ilist_traits<MachineBasicBlock>;
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void setParent(MachineBasicBlock *P) { Parent = P; }
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/// MachineInstr ctor - This constructor creates a copy of the given
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/// MachineInstr in the given MachineFunction.
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MachineInstr(MachineFunction &, const MachineInstr &);
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// TID NULL and no operands.
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MachineInstr();
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// The next two constructors have DebugLoc and non-DebugLoc versions;
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// over time, the non-DebugLoc versions should be phased out and eventually
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// removed.
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDesc. The version with a DebugLoc should be preferred.
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explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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/// block. The version with a DebugLoc should be preferred.
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///
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MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDesc. An explicit DebugLoc is supplied.
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explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
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bool NoImp = false);
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that
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/// the MachineInstr is created and added to the end of the specified basic
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/// block.
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///
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MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
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const TargetInstrDesc &TID);
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~MachineInstr();
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// MachineInstrs are pool-allocated and owned by MachineFunction.
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friend class MachineFunction;
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public:
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const MachineBasicBlock* getParent() const { return Parent; }
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MachineBasicBlock* getParent() { return Parent; }
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/// getAsmPrinterFlags - Return the asm printer flags bitvector.
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///
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unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
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/// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
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///
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bool getAsmPrinterFlag(CommentFlag Flag) const {
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return AsmPrinterFlags & Flag;
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}
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/// setAsmPrinterFlag - Set a flag for the AsmPrinter.
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///
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void setAsmPrinterFlag(CommentFlag Flag) {
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AsmPrinterFlags |= (unsigned short)Flag;
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}
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/// getDebugLoc - Returns the debug location id of this MachineInstr.
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///
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DebugLoc getDebugLoc() const { return debugLoc; }
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/// getDesc - Returns the target instruction descriptor of this
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/// MachineInstr.
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const TargetInstrDesc &getDesc() const { return *TID; }
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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int getOpcode() const { return TID->Opcode; }
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/// Access to explicit operands of the instruction.
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///
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unsigned getNumOperands() const { return (unsigned)Operands.size(); }
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const MachineOperand& getOperand(unsigned i) const {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return Operands[i];
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}
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MachineOperand& getOperand(unsigned i) {
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assert(i < getNumOperands() && "getOperand() out of range!");
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return Operands[i];
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}
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/// getNumExplicitOperands - Returns the number of non-implicit operands.
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///
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unsigned getNumExplicitOperands() const;
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/// Access to memory operands of the instruction
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mmo_iterator memoperands_begin() const { return MemRefs; }
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mmo_iterator memoperands_end() const { return MemRefsEnd; }
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bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
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/// hasOneMemOperand - Return true if this instruction has exactly one
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/// MachineMemOperand.
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bool hasOneMemOperand() const {
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return MemRefsEnd - MemRefs == 1;
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}
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enum MICheckType {
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CheckDefs, // Check all operands for equality
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IgnoreDefs, // Ignore all definitions
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IgnoreVRegDefs // Ignore virtual register definitions
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};
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/// isIdenticalTo - Return true if this instruction is identical to (same
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/// opcode and same operands as) the specified instruction.
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bool isIdenticalTo(const MachineInstr *Other,
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MICheckType Check = CheckDefs) const;
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/// removeFromParent - This method unlinks 'this' from the containing basic
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/// block, and returns it, but does not delete it.
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MachineInstr *removeFromParent();
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/// eraseFromParent - This method unlinks 'this' from the containing basic
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/// block and deletes it.
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void eraseFromParent();
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/// isLabel - Returns true if the MachineInstr represents a label.
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///
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bool isLabel() const {
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return getOpcode() == TargetOpcode::DBG_LABEL ||
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getOpcode() == TargetOpcode::EH_LABEL ||
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getOpcode() == TargetOpcode::GC_LABEL;
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}
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bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
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bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
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bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
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bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
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bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
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bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
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bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
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bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
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bool isExtractSubreg() const {
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return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
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}
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bool isInsertSubreg() const {
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return getOpcode() == TargetOpcode::INSERT_SUBREG;
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}
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bool isSubregToReg() const {
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return getOpcode() == TargetOpcode::SUBREG_TO_REG;
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}
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/// readsRegister - Return true if the MachineInstr reads the specified
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/// register. If TargetRegisterInfo is passed, then it also checks if there
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/// is a read of a super-register.
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bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
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return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
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}
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/// killsRegister - Return true if the MachineInstr kills the specified
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/// register. If TargetRegisterInfo is passed, then it also checks if there is
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/// a kill of a super-register.
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bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
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return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
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}
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/// modifiesRegister - Return true if the MachineInstr modifies the
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/// specified register. If TargetRegisterInfo is passed, then it also checks
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/// if there is a def of a super-register.
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bool modifiesRegister(unsigned Reg,
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const TargetRegisterInfo *TRI = NULL) const {
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return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
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}
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/// registerDefIsDead - Returns true if the register is dead in this machine
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/// instruction. If TargetRegisterInfo is passed, then it also checks
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/// if there is a dead def of a super-register.
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bool registerDefIsDead(unsigned Reg,
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const TargetRegisterInfo *TRI = NULL) const {
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return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
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}
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/// findRegisterUseOperandIdx() - Returns the operand index that is a use of
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/// the specific register or -1 if it is not found. It further tightens
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/// the search criteria to a use that kills the register if isKill is true.
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int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
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const TargetRegisterInfo *TRI = NULL) const;
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/// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
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/// a pointer to the MachineOperand rather than an index.
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MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
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const TargetRegisterInfo *TRI = NULL) {
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int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
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return (Idx == -1) ? NULL : &getOperand(Idx);
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}
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/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
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/// the specified register or -1 if it is not found. If isDead is true, defs
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/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
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/// also checks if there is a def of a super-register.
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int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
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const TargetRegisterInfo *TRI = NULL) const;
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/// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
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/// a pointer to the MachineOperand rather than an index.
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MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
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const TargetRegisterInfo *TRI = NULL) {
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int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
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return (Idx == -1) ? NULL : &getOperand(Idx);
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}
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/// findFirstPredOperandIdx() - Find the index of the first operand in the
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/// operand list that is used to represent the predicate. It returns -1 if
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/// none is found.
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int findFirstPredOperandIdx() const;
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/// isRegTiedToUseOperand - Given the index of a register def operand,
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/// check if the register def is tied to a source operand, due to either
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/// two-address elimination or inline assembly constraints. Returns the
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/// first tied use operand index by reference is UseOpIdx is not null.
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bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
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/// isRegTiedToDefOperand - Return true if the use operand of the specified
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/// index is tied to an def operand. It also returns the def operand index by
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/// reference if DefOpIdx is not null.
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bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
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/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
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///
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void copyKillDeadInfo(const MachineInstr *MI);
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/// copyPredicates - Copies predicate operand(s) from MI.
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void copyPredicates(const MachineInstr *MI);
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/// addRegisterKilled - We have determined MI kills a register. Look for the
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/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
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/// add a implicit operand if it's not found. Returns true if the operand
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/// exists / is added.
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bool addRegisterKilled(unsigned IncomingReg,
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const TargetRegisterInfo *RegInfo,
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bool AddIfNotFound = false);
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/// addRegisterDead - We have determined MI defined a register without a use.
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/// Look for the operand that defines it and mark it as IsDead. If
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/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
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/// true if the operand exists / is added.
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bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
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bool AddIfNotFound = false);
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/// addRegisterDefined - We have determined MI defines a register. Make sure
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/// there is an operand defining Reg.
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void addRegisterDefined(unsigned IncomingReg,
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const TargetRegisterInfo *RegInfo);
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/// isSafeToMove - Return true if it is safe to move this instruction. If
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/// SawStore is set to true, it means that there is a store (or call) between
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/// the instruction's location and its intended destination.
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bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
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bool &SawStore) const;
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/// isSafeToReMat - Return true if it's safe to rematerialize the specified
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/// instruction which defined the specified register instead of copying it.
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bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
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unsigned DstReg) const;
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/// hasVolatileMemoryRef - Return true if this instruction may have a
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/// volatile memory reference, or if the information describing the
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/// memory reference is not available. Return false if it is known to
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/// have no volatile memory references.
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bool hasVolatileMemoryRef() const;
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/// isInvariantLoad - Return true if this instruction is loading from a
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/// location whose value is invariant across the function. For example,
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/// loading a value from the constant pool or from the argument area of
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/// a function if it does not change. This should only return true of *all*
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/// loads the instruction does are invariant (if it does multiple loads).
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bool isInvariantLoad(AliasAnalysis *AA) const;
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/// isConstantValuePHI - If the specified instruction is a PHI that always
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/// merges together the same virtual register, return the register, otherwise
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/// return 0.
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unsigned isConstantValuePHI() const;
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//
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// Debugging support
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//
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void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
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void dump() const;
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//===--------------------------------------------------------------------===//
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// Accessors used to build up machine instructions.
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/// addOperand - Add the specified operand to the instruction. If it is an
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/// implicit operand, it is added to the end of the operand list. If it is
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/// an explicit operand it is added at the end of the explicit operand list
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/// (before the first implicit operand).
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void addOperand(const MachineOperand &Op);
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/// setDesc - Replace the instruction descriptor (thus opcode) of
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/// the current instruction with a new one.
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///
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void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
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/// setDebugLoc - Replace current source information with new such.
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/// Avoid using this, the constructor argument is preferable.
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///
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void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// fewer operand than it started with.
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///
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void RemoveOperand(unsigned i);
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/// addMemOperand - Add a MachineMemOperand to the machine instruction.
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/// This function should be used only occasionally. The setMemRefs function
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/// is the primary method for setting up a MachineInstr's MemRefs list.
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void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
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/// setMemRefs - Assign this MachineInstr's memory reference descriptor
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/// list. This does not transfer ownership.
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void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
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MemRefs = NewMemRefs;
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MemRefsEnd = NewMemRefsEnd;
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}
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private:
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/// getRegInfo - If this instruction is embedded into a MachineFunction,
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/// return the MachineRegisterInfo object for the current function, otherwise
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/// return null.
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MachineRegisterInfo *getRegInfo();
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/// addImplicitDefUseOperands - Add all implicit def and use operands to
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/// this instruction.
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void addImplicitDefUseOperands();
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/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
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/// this instruction from their respective use lists. This requires that the
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/// operands already be on their use lists.
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void RemoveRegOperandsFromUseLists();
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/// AddRegOperandsToUseLists - Add all of the register operands in
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/// this instruction from their respective use lists. This requires that the
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/// operands not be on their use lists yet.
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void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
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};
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/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
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/// MachineInstr* by *value* of the instruction rather than by pointer value.
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/// The hashing and equality testing functions ignore definitions so this is
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/// useful for CSE, etc.
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struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
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static inline MachineInstr *getEmptyKey() {
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return 0;
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}
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static inline MachineInstr *getTombstoneKey() {
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return reinterpret_cast<MachineInstr*>(-1);
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}
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static unsigned getHashValue(const MachineInstr* const &MI);
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static bool isEqual(const MachineInstr* const &LHS,
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const MachineInstr* const &RHS) {
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if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
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LHS == getEmptyKey() || LHS == getTombstoneKey())
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return LHS == RHS;
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return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
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}
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};
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//===----------------------------------------------------------------------===//
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// Debugging Support
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inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
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MI.print(OS);
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return OS;
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}
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} // End llvm namespace
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#endif
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