mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97261 91177308-0d34-0410-b5e6-96231b3b80d8
1509 lines
54 KiB
C++
1509 lines
54 KiB
C++
//===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a linear scan register allocator.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "Spiller.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/EquivalenceClasses.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <set>
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#include <queue>
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#include <memory>
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#include <cmath>
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using namespace llvm;
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STATISTIC(NumIters , "Number of iterations performed");
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STATISTIC(NumBacktracks, "Number of times we had to backtrack");
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STATISTIC(NumCoalesce, "Number of copies coalesced");
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STATISTIC(NumDowngrade, "Number of registers downgraded");
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static cl::opt<bool>
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NewHeuristic("new-spilling-heuristic",
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cl::desc("Use new spilling heuristic"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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PreSplitIntervals("pre-alloc-split",
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cl::desc("Pre-register allocation live interval splitting"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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TrivCoalesceEnds("trivial-coalesce-ends",
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cl::desc("Attempt trivial coalescing of interval ends"),
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cl::init(false), cl::Hidden);
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static RegisterRegAlloc
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linearscanRegAlloc("linearscan", "linear scan register allocator",
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createLinearScanRegisterAllocator);
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namespace {
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// When we allocate a register, add it to a fixed-size queue of
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// registers to skip in subsequent allocations. This trades a small
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// amount of register pressure and increased spills for flexibility in
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// the post-pass scheduler.
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//
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// Note that in a the number of registers used for reloading spills
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// will be one greater than the value of this option.
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//
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// One big limitation of this is that it doesn't differentiate between
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// different register classes. So on x86-64, if there is xmm register
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// pressure, it can caused fewer GPRs to be held in the queue.
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static cl::opt<unsigned>
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NumRecentlyUsedRegs("linearscan-skip-count",
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cl::desc("Number of registers for linearscan to remember to skip."),
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cl::init(0),
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cl::Hidden);
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struct RALinScan : public MachineFunctionPass {
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static char ID;
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RALinScan() : MachineFunctionPass(&ID) {
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// Initialize the queue to record recently-used registers.
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if (NumRecentlyUsedRegs > 0)
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RecentRegs.resize(NumRecentlyUsedRegs, 0);
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RecentNext = RecentRegs.begin();
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}
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typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
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typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
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private:
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/// RelatedRegClasses - This structure is built the first time a function is
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/// compiled, and keeps track of which register classes have registers that
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/// belong to multiple classes or have aliases that are in other classes.
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EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
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DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
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// NextReloadMap - For each register in the map, it maps to the another
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// register which is defined by a reload from the same stack slot and
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// both reloads are in the same basic block.
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DenseMap<unsigned, unsigned> NextReloadMap;
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// DowngradedRegs - A set of registers which are being "downgraded", i.e.
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// un-favored for allocation.
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SmallSet<unsigned, 8> DowngradedRegs;
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// DowngradeMap - A map from virtual registers to physical registers being
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// downgraded for the virtual registers.
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DenseMap<unsigned, unsigned> DowngradeMap;
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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BitVector allocatableRegs_;
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LiveIntervals* li_;
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LiveStacks* ls_;
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const MachineLoopInfo *loopInfo;
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/// handled_ - Intervals are added to the handled_ set in the order of their
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/// start value. This is uses for backtracking.
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std::vector<LiveInterval*> handled_;
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/// fixed_ - Intervals that correspond to machine registers.
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///
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IntervalPtrs fixed_;
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/// active_ - Intervals that are currently being processed, and which have a
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/// live range active for the current point.
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IntervalPtrs active_;
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/// inactive_ - Intervals that are currently being processed, but which have
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/// a hold at the current point.
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IntervalPtrs inactive_;
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typedef std::priority_queue<LiveInterval*,
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SmallVector<LiveInterval*, 64>,
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greater_ptr<LiveInterval> > IntervalHeap;
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IntervalHeap unhandled_;
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/// regUse_ - Tracks register usage.
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SmallVector<unsigned, 32> regUse_;
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SmallVector<unsigned, 32> regUseBackUp_;
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/// vrm_ - Tracks register assignments.
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VirtRegMap* vrm_;
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std::auto_ptr<VirtRegRewriter> rewriter_;
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std::auto_ptr<Spiller> spiller_;
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// The queue of recently-used registers.
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SmallVector<unsigned, 4> RecentRegs;
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SmallVector<unsigned, 4>::iterator RecentNext;
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// Record that we just picked this register.
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void recordRecentlyUsed(unsigned reg) {
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assert(reg != 0 && "Recently used register is NOREG!");
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if (!RecentRegs.empty()) {
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*RecentNext++ = reg;
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if (RecentNext == RecentRegs.end())
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RecentNext = RecentRegs.begin();
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}
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}
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public:
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virtual const char* getPassName() const {
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return "Linear Scan Register Allocator";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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if (StrongPHIElim)
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AU.addRequiredID(StrongPHIEliminationID);
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// Make sure PassManager knows which analyses to make available
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// to coalescing and which analyses coalescing invalidates.
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AU.addRequiredTransitive<RegisterCoalescer>();
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AU.addRequired<CalculateSpillWeights>();
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if (PreSplitIntervals)
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AU.addRequiredID(PreAllocSplittingID);
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - register allocate the whole function
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bool runOnMachineFunction(MachineFunction&);
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// Determine if we skip this register due to its being recently used.
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bool isRecentlyUsed(unsigned reg) const {
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return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
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RecentRegs.end();
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}
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private:
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/// linearScan - the linear scan algorithm
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void linearScan();
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/// initIntervalSets - initialize the interval sets.
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///
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void initIntervalSets();
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/// processActiveIntervals - expire old intervals and move non-overlapping
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/// ones to the inactive list.
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void processActiveIntervals(SlotIndex CurPoint);
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/// processInactiveIntervals - expire old intervals and move overlapping
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/// ones to the active list.
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void processInactiveIntervals(SlotIndex CurPoint);
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/// hasNextReloadInterval - Return the next liveinterval that's being
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/// defined by a reload from the same SS as the specified one.
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LiveInterval *hasNextReloadInterval(LiveInterval *cur);
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/// DowngradeRegister - Downgrade a register for allocation.
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void DowngradeRegister(LiveInterval *li, unsigned Reg);
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/// UpgradeRegister - Upgrade a register for allocation.
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void UpgradeRegister(unsigned Reg);
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/// assignRegOrStackSlotAtInterval - assign a register if one
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/// is available, or spill.
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void assignRegOrStackSlotAtInterval(LiveInterval* cur);
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void updateSpillWeights(std::vector<float> &Weights,
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unsigned reg, float weight,
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const TargetRegisterClass *RC);
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/// findIntervalsToSpill - Determine the intervals to spill for the
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/// specified interval. It's passed the physical registers whose spill
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/// weight is the lowest among all the registers whose live intervals
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/// conflict with the interval.
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void findIntervalsToSpill(LiveInterval *cur,
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std::vector<std::pair<unsigned,float> > &Candidates,
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unsigned NumCands,
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SmallVector<LiveInterval*, 8> &SpillIntervals);
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/// attemptTrivialCoalescing - If a simple interval is defined by a copy,
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/// try allocate the definition the same register as the source register
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/// if the register is not defined during live time of the interval. This
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/// eliminate a copy. This is used to coalesce copies which were not
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/// coalesced away before allocation either due to dest and src being in
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/// different register classes or because the coalescer was overly
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/// conservative.
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unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
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///
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/// Register usage / availability tracking helpers.
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///
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void initRegUses() {
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regUse_.resize(tri_->getNumRegs(), 0);
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regUseBackUp_.resize(tri_->getNumRegs(), 0);
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}
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void finalizeRegUses() {
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#ifndef NDEBUG
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// Verify all the registers are "freed".
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bool Error = false;
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for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
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if (regUse_[i] != 0) {
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dbgs() << tri_->getName(i) << " is still in use!\n";
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Error = true;
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}
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}
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if (Error)
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llvm_unreachable(0);
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#endif
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regUse_.clear();
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regUseBackUp_.clear();
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}
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void addRegUse(unsigned physReg) {
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assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
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"should be physical register!");
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++regUse_[physReg];
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for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
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++regUse_[*as];
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}
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void delRegUse(unsigned physReg) {
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assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
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"should be physical register!");
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assert(regUse_[physReg] != 0);
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--regUse_[physReg];
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for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
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assert(regUse_[*as] != 0);
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--regUse_[*as];
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}
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}
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bool isRegAvail(unsigned physReg) const {
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assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
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"should be physical register!");
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return regUse_[physReg] == 0;
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}
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void backUpRegUses() {
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regUseBackUp_ = regUse_;
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}
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void restoreRegUses() {
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regUse_ = regUseBackUp_;
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}
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///
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/// Register handling helpers.
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///
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/// getFreePhysReg - return a free physical register for this virtual
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/// register interval if we have one, otherwise return 0.
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unsigned getFreePhysReg(LiveInterval* cur);
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unsigned getFreePhysReg(LiveInterval* cur,
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const TargetRegisterClass *RC,
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unsigned MaxInactiveCount,
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SmallVector<unsigned, 256> &inactiveCounts,
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bool SkipDGRegs);
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void ComputeRelatedRegClasses();
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template <typename ItTy>
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void printIntervals(const char* const str, ItTy i, ItTy e) const {
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DEBUG({
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if (str)
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dbgs() << str << " intervals:\n";
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for (; i != e; ++i) {
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dbgs() << "\t" << *i->first << " -> ";
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unsigned reg = i->first->reg;
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if (TargetRegisterInfo::isVirtualRegister(reg))
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reg = vrm_->getPhys(reg);
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dbgs() << tri_->getName(reg) << '\n';
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}
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});
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}
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};
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char RALinScan::ID = 0;
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}
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static RegisterPass<RALinScan>
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X("linearscan-regalloc", "Linear Scan Register Allocator");
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void RALinScan::ComputeRelatedRegClasses() {
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// First pass, add all reg classes to the union, and determine at least one
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// reg class that each register is in.
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bool HasAliases = false;
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for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
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E = tri_->regclass_end(); RCI != E; ++RCI) {
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RelatedRegClasses.insert(*RCI);
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for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
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I != E; ++I) {
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HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
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const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
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if (PRC) {
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// Already processed this register. Just make sure we know that
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// multiple register classes share a register.
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RelatedRegClasses.unionSets(PRC, *RCI);
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} else {
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PRC = *RCI;
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}
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}
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}
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// Second pass, now that we know conservatively what register classes each reg
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// belongs to, add info about aliases. We don't need to do this for targets
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// without register aliases.
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if (HasAliases)
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for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
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I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
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I != E; ++I)
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for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
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RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
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}
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/// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
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/// allocate the definition the same register as the source register if the
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/// register is not defined during live time of the interval. If the interval is
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/// killed by a copy, try to use the destination register. This eliminates a
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/// copy. This is used to coalesce copies which were not coalesced away before
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/// allocation either due to dest and src being in different register classes or
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/// because the coalescer was overly conservative.
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unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
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unsigned Preference = vrm_->getRegAllocPref(cur.reg);
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if ((Preference && Preference == Reg) || !cur.containsOneValue())
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return Reg;
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// We cannot handle complicated live ranges. Simple linear stuff only.
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if (cur.ranges.size() != 1)
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return Reg;
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const LiveRange &range = cur.ranges.front();
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VNInfo *vni = range.valno;
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if (vni->isUnused())
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return Reg;
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unsigned CandReg;
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{
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MachineInstr *CopyMI;
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unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
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if (vni->def != SlotIndex() && vni->isDefAccurate() &&
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(CopyMI = li_->getInstructionFromIndex(vni->def)) &&
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tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
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// Defined by a copy, try to extend SrcReg forward
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CandReg = SrcReg;
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else if (TrivCoalesceEnds &&
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(CopyMI =
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li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
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tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
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cur.reg == SrcReg)
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// Only used by a copy, try to extend DstReg backwards
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CandReg = DstReg;
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else
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return Reg;
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}
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if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
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if (!vrm_->isAssignedReg(CandReg))
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return Reg;
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CandReg = vrm_->getPhys(CandReg);
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}
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if (Reg == CandReg)
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return Reg;
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const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
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if (!RC->contains(CandReg))
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return Reg;
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if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
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return Reg;
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// Try to coalesce.
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DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
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<< '\n');
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vrm_->clearVirt(cur.reg);
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vrm_->assignVirt2Phys(cur.reg, CandReg);
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++NumCoalesce;
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return CandReg;
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}
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bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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mri_ = &fn.getRegInfo();
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tm_ = &fn.getTarget();
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tri_ = tm_->getRegisterInfo();
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tii_ = tm_->getInstrInfo();
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allocatableRegs_ = tri_->getAllocatableSet(fn);
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li_ = &getAnalysis<LiveIntervals>();
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ls_ = &getAnalysis<LiveStacks>();
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loopInfo = &getAnalysis<MachineLoopInfo>();
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// We don't run the coalescer here because we have no reason to
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// interact with it. If the coalescer requires interaction, it
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// won't do anything. If it doesn't require interaction, we assume
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// it was run as a separate pass.
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// If this is the first function compiled, compute the related reg classes.
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if (RelatedRegClasses.empty())
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ComputeRelatedRegClasses();
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// Also resize register usage trackers.
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initRegUses();
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vrm_ = &getAnalysis<VirtRegMap>();
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if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
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spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
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initIntervalSets();
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linearScan();
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// Rewrite spill code and update the PhysRegsUsed set.
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rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
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assert(unhandled_.empty() && "Unhandled live intervals remain!");
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finalizeRegUses();
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|
fixed_.clear();
|
|
active_.clear();
|
|
inactive_.clear();
|
|
handled_.clear();
|
|
NextReloadMap.clear();
|
|
DowngradedRegs.clear();
|
|
DowngradeMap.clear();
|
|
spiller_.reset(0);
|
|
|
|
return true;
|
|
}
|
|
|
|
/// initIntervalSets - initialize the interval sets.
|
|
///
|
|
void RALinScan::initIntervalSets()
|
|
{
|
|
assert(unhandled_.empty() && fixed_.empty() &&
|
|
active_.empty() && inactive_.empty() &&
|
|
"interval sets should be empty on initialization");
|
|
|
|
handled_.reserve(li_->getNumIntervals());
|
|
|
|
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
|
|
if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
|
|
if (!i->second->empty()) {
|
|
mri_->setPhysRegUsed(i->second->reg);
|
|
fixed_.push_back(std::make_pair(i->second, i->second->begin()));
|
|
}
|
|
} else {
|
|
if (i->second->empty()) {
|
|
assignRegOrStackSlotAtInterval(i->second);
|
|
}
|
|
else
|
|
unhandled_.push(i->second);
|
|
}
|
|
}
|
|
}
|
|
|
|
void RALinScan::linearScan() {
|
|
// linear scan algorithm
|
|
DEBUG({
|
|
dbgs() << "********** LINEAR SCAN **********\n"
|
|
<< "********** Function: "
|
|
<< mf_->getFunction()->getName() << '\n';
|
|
printIntervals("fixed", fixed_.begin(), fixed_.end());
|
|
});
|
|
|
|
while (!unhandled_.empty()) {
|
|
// pick the interval with the earliest start point
|
|
LiveInterval* cur = unhandled_.top();
|
|
unhandled_.pop();
|
|
++NumIters;
|
|
DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
|
|
|
|
assert(!cur->empty() && "Empty interval in unhandled set.");
|
|
|
|
processActiveIntervals(cur->beginIndex());
|
|
processInactiveIntervals(cur->beginIndex());
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
|
|
"Can only allocate virtual registers!");
|
|
|
|
// Allocating a virtual register. try to find a free
|
|
// physical register or spill an interval (possibly this one) in order to
|
|
// assign it one.
|
|
assignRegOrStackSlotAtInterval(cur);
|
|
|
|
DEBUG({
|
|
printIntervals("active", active_.begin(), active_.end());
|
|
printIntervals("inactive", inactive_.begin(), inactive_.end());
|
|
});
|
|
}
|
|
|
|
// Expire any remaining active intervals
|
|
while (!active_.empty()) {
|
|
IntervalPtr &IP = active_.back();
|
|
unsigned reg = IP.first->reg;
|
|
DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
|
|
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
|
|
"Can only allocate virtual registers!");
|
|
reg = vrm_->getPhys(reg);
|
|
delRegUse(reg);
|
|
active_.pop_back();
|
|
}
|
|
|
|
// Expire any remaining inactive intervals
|
|
DEBUG({
|
|
for (IntervalPtrs::reverse_iterator
|
|
i = inactive_.rbegin(); i != inactive_.rend(); ++i)
|
|
dbgs() << "\tinterval " << *i->first << " expired\n";
|
|
});
|
|
inactive_.clear();
|
|
|
|
// Add live-ins to every BB except for entry. Also perform trivial coalescing.
|
|
MachineFunction::iterator EntryMBB = mf_->begin();
|
|
SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
|
|
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
|
|
LiveInterval &cur = *i->second;
|
|
unsigned Reg = 0;
|
|
bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
|
|
if (isPhys)
|
|
Reg = cur.reg;
|
|
else if (vrm_->isAssignedReg(cur.reg))
|
|
Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
|
|
if (!Reg)
|
|
continue;
|
|
// Ignore splited live intervals.
|
|
if (!isPhys && vrm_->getPreSplitReg(cur.reg))
|
|
continue;
|
|
|
|
for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
|
|
I != E; ++I) {
|
|
const LiveRange &LR = *I;
|
|
if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
|
|
for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
|
|
if (LiveInMBBs[i] != EntryMBB) {
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
|
|
"Adding a virtual register to livein set?");
|
|
LiveInMBBs[i]->addLiveIn(Reg);
|
|
}
|
|
LiveInMBBs.clear();
|
|
}
|
|
}
|
|
}
|
|
|
|
DEBUG(dbgs() << *vrm_);
|
|
|
|
// Look for physical registers that end up not being allocated even though
|
|
// register allocator had to spill other registers in its register class.
|
|
if (ls_->getNumIntervals() == 0)
|
|
return;
|
|
if (!vrm_->FindUnusedRegisters(li_))
|
|
return;
|
|
}
|
|
|
|
/// processActiveIntervals - expire old intervals and move non-overlapping ones
|
|
/// to the inactive list.
|
|
void RALinScan::processActiveIntervals(SlotIndex CurPoint)
|
|
{
|
|
DEBUG(dbgs() << "\tprocessing active intervals:\n");
|
|
|
|
for (unsigned i = 0, e = active_.size(); i != e; ++i) {
|
|
LiveInterval *Interval = active_[i].first;
|
|
LiveInterval::iterator IntervalPos = active_[i].second;
|
|
unsigned reg = Interval->reg;
|
|
|
|
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
|
|
|
|
if (IntervalPos == Interval->end()) { // Remove expired intervals.
|
|
DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
|
|
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
|
|
"Can only allocate virtual registers!");
|
|
reg = vrm_->getPhys(reg);
|
|
delRegUse(reg);
|
|
|
|
// Pop off the end of the list.
|
|
active_[i] = active_.back();
|
|
active_.pop_back();
|
|
--i; --e;
|
|
|
|
} else if (IntervalPos->start > CurPoint) {
|
|
// Move inactive intervals to inactive list.
|
|
DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
|
|
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
|
|
"Can only allocate virtual registers!");
|
|
reg = vrm_->getPhys(reg);
|
|
delRegUse(reg);
|
|
// add to inactive.
|
|
inactive_.push_back(std::make_pair(Interval, IntervalPos));
|
|
|
|
// Pop off the end of the list.
|
|
active_[i] = active_.back();
|
|
active_.pop_back();
|
|
--i; --e;
|
|
} else {
|
|
// Otherwise, just update the iterator position.
|
|
active_[i].second = IntervalPos;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// processInactiveIntervals - expire old intervals and move overlapping
|
|
/// ones to the active list.
|
|
void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
|
|
{
|
|
DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
|
|
|
|
for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
|
|
LiveInterval *Interval = inactive_[i].first;
|
|
LiveInterval::iterator IntervalPos = inactive_[i].second;
|
|
unsigned reg = Interval->reg;
|
|
|
|
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
|
|
|
|
if (IntervalPos == Interval->end()) { // remove expired intervals.
|
|
DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
|
|
|
|
// Pop off the end of the list.
|
|
inactive_[i] = inactive_.back();
|
|
inactive_.pop_back();
|
|
--i; --e;
|
|
} else if (IntervalPos->start <= CurPoint) {
|
|
// move re-activated intervals in active list
|
|
DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
|
|
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
|
|
"Can only allocate virtual registers!");
|
|
reg = vrm_->getPhys(reg);
|
|
addRegUse(reg);
|
|
// add to active
|
|
active_.push_back(std::make_pair(Interval, IntervalPos));
|
|
|
|
// Pop off the end of the list.
|
|
inactive_[i] = inactive_.back();
|
|
inactive_.pop_back();
|
|
--i; --e;
|
|
} else {
|
|
// Otherwise, just update the iterator position.
|
|
inactive_[i].second = IntervalPos;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// updateSpillWeights - updates the spill weights of the specifed physical
|
|
/// register and its weight.
|
|
void RALinScan::updateSpillWeights(std::vector<float> &Weights,
|
|
unsigned reg, float weight,
|
|
const TargetRegisterClass *RC) {
|
|
SmallSet<unsigned, 4> Processed;
|
|
SmallSet<unsigned, 4> SuperAdded;
|
|
SmallVector<unsigned, 4> Supers;
|
|
Weights[reg] += weight;
|
|
Processed.insert(reg);
|
|
for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
|
|
Weights[*as] += weight;
|
|
Processed.insert(*as);
|
|
if (tri_->isSubRegister(*as, reg) &&
|
|
SuperAdded.insert(*as) &&
|
|
RC->contains(*as)) {
|
|
Supers.push_back(*as);
|
|
}
|
|
}
|
|
|
|
// If the alias is a super-register, and the super-register is in the
|
|
// register class we are trying to allocate. Then add the weight to all
|
|
// sub-registers of the super-register even if they are not aliases.
|
|
// e.g. allocating for GR32, bh is not used, updating bl spill weight.
|
|
// bl should get the same spill weight otherwise it will be choosen
|
|
// as a spill candidate since spilling bh doesn't make ebx available.
|
|
for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
|
|
for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
|
|
if (!Processed.count(*sr))
|
|
Weights[*sr] += weight;
|
|
}
|
|
}
|
|
|
|
static
|
|
RALinScan::IntervalPtrs::iterator
|
|
FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
|
|
for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
|
|
I != E; ++I)
|
|
if (I->first == LI) return I;
|
|
return IP.end();
|
|
}
|
|
|
|
static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
|
|
for (unsigned i = 0, e = V.size(); i != e; ++i) {
|
|
RALinScan::IntervalPtr &IP = V[i];
|
|
LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
|
|
IP.second, Point);
|
|
if (I != IP.first->begin()) --I;
|
|
IP.second = I;
|
|
}
|
|
}
|
|
|
|
/// addStackInterval - Create a LiveInterval for stack if the specified live
|
|
/// interval has been spilled.
|
|
static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
|
|
LiveIntervals *li_,
|
|
MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
|
|
int SS = vrm_.getStackSlot(cur->reg);
|
|
if (SS == VirtRegMap::NO_STACK_SLOT)
|
|
return;
|
|
|
|
const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
|
|
LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
|
|
|
|
VNInfo *VNI;
|
|
if (SI.hasAtLeastOneValue())
|
|
VNI = SI.getValNumInfo(0);
|
|
else
|
|
VNI = SI.getNextValue(SlotIndex(), 0, false,
|
|
ls_->getVNInfoAllocator());
|
|
|
|
LiveInterval &RI = li_->getInterval(cur->reg);
|
|
// FIXME: This may be overly conservative.
|
|
SI.MergeRangesInAsValue(RI, VNI);
|
|
}
|
|
|
|
/// getConflictWeight - Return the number of conflicts between cur
|
|
/// live interval and defs and uses of Reg weighted by loop depthes.
|
|
static
|
|
float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
|
|
MachineRegisterInfo *mri_,
|
|
const MachineLoopInfo *loopInfo) {
|
|
float Conflicts = 0;
|
|
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
|
|
E = mri_->reg_end(); I != E; ++I) {
|
|
MachineInstr *MI = &*I;
|
|
if (cur->liveAt(li_->getInstructionIndex(MI))) {
|
|
unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
|
|
Conflicts += powf(10.0f, (float)loopDepth);
|
|
}
|
|
}
|
|
return Conflicts;
|
|
}
|
|
|
|
/// findIntervalsToSpill - Determine the intervals to spill for the
|
|
/// specified interval. It's passed the physical registers whose spill
|
|
/// weight is the lowest among all the registers whose live intervals
|
|
/// conflict with the interval.
|
|
void RALinScan::findIntervalsToSpill(LiveInterval *cur,
|
|
std::vector<std::pair<unsigned,float> > &Candidates,
|
|
unsigned NumCands,
|
|
SmallVector<LiveInterval*, 8> &SpillIntervals) {
|
|
// We have figured out the *best* register to spill. But there are other
|
|
// registers that are pretty good as well (spill weight within 3%). Spill
|
|
// the one that has fewest defs and uses that conflict with cur.
|
|
float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
|
|
SmallVector<LiveInterval*, 8> SLIs[3];
|
|
|
|
DEBUG({
|
|
dbgs() << "\tConsidering " << NumCands << " candidates: ";
|
|
for (unsigned i = 0; i != NumCands; ++i)
|
|
dbgs() << tri_->getName(Candidates[i].first) << " ";
|
|
dbgs() << "\n";
|
|
});
|
|
|
|
// Calculate the number of conflicts of each candidate.
|
|
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
|
|
unsigned Reg = i->first->reg;
|
|
unsigned PhysReg = vrm_->getPhys(Reg);
|
|
if (!cur->overlapsFrom(*i->first, i->second))
|
|
continue;
|
|
for (unsigned j = 0; j < NumCands; ++j) {
|
|
unsigned Candidate = Candidates[j].first;
|
|
if (tri_->regsOverlap(PhysReg, Candidate)) {
|
|
if (NumCands > 1)
|
|
Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
|
|
SLIs[j].push_back(i->first);
|
|
}
|
|
}
|
|
}
|
|
|
|
for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
|
|
unsigned Reg = i->first->reg;
|
|
unsigned PhysReg = vrm_->getPhys(Reg);
|
|
if (!cur->overlapsFrom(*i->first, i->second-1))
|
|
continue;
|
|
for (unsigned j = 0; j < NumCands; ++j) {
|
|
unsigned Candidate = Candidates[j].first;
|
|
if (tri_->regsOverlap(PhysReg, Candidate)) {
|
|
if (NumCands > 1)
|
|
Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
|
|
SLIs[j].push_back(i->first);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Which is the best candidate?
|
|
unsigned BestCandidate = 0;
|
|
float MinConflicts = Conflicts[0];
|
|
for (unsigned i = 1; i != NumCands; ++i) {
|
|
if (Conflicts[i] < MinConflicts) {
|
|
BestCandidate = i;
|
|
MinConflicts = Conflicts[i];
|
|
}
|
|
}
|
|
|
|
std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
|
|
std::back_inserter(SpillIntervals));
|
|
}
|
|
|
|
namespace {
|
|
struct WeightCompare {
|
|
private:
|
|
const RALinScan &Allocator;
|
|
|
|
public:
|
|
WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
|
|
|
|
typedef std::pair<unsigned, float> RegWeightPair;
|
|
bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
|
|
return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
|
|
}
|
|
};
|
|
}
|
|
|
|
static bool weightsAreClose(float w1, float w2) {
|
|
if (!NewHeuristic)
|
|
return false;
|
|
|
|
float diff = w1 - w2;
|
|
if (diff <= 0.02f) // Within 0.02f
|
|
return true;
|
|
return (diff / w2) <= 0.05f; // Within 5%.
|
|
}
|
|
|
|
LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
|
|
DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
|
|
if (I == NextReloadMap.end())
|
|
return 0;
|
|
return &li_->getInterval(I->second);
|
|
}
|
|
|
|
void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
|
|
bool isNew = DowngradedRegs.insert(Reg);
|
|
isNew = isNew; // Silence compiler warning.
|
|
assert(isNew && "Multiple reloads holding the same register?");
|
|
DowngradeMap.insert(std::make_pair(li->reg, Reg));
|
|
for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
|
|
isNew = DowngradedRegs.insert(*AS);
|
|
isNew = isNew; // Silence compiler warning.
|
|
assert(isNew && "Multiple reloads holding the same register?");
|
|
DowngradeMap.insert(std::make_pair(li->reg, *AS));
|
|
}
|
|
++NumDowngrade;
|
|
}
|
|
|
|
void RALinScan::UpgradeRegister(unsigned Reg) {
|
|
if (Reg) {
|
|
DowngradedRegs.erase(Reg);
|
|
for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
|
|
DowngradedRegs.erase(*AS);
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
struct LISorter {
|
|
bool operator()(LiveInterval* A, LiveInterval* B) {
|
|
return A->beginIndex() < B->beginIndex();
|
|
}
|
|
};
|
|
}
|
|
|
|
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
|
|
/// spill.
|
|
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
|
|
DEBUG(dbgs() << "\tallocating current interval: ");
|
|
|
|
// This is an implicitly defined live interval, just assign any register.
|
|
const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
|
|
if (cur->empty()) {
|
|
unsigned physReg = vrm_->getRegAllocPref(cur->reg);
|
|
if (!physReg)
|
|
physReg = *RC->allocation_order_begin(*mf_);
|
|
DEBUG(dbgs() << tri_->getName(physReg) << '\n');
|
|
// Note the register is not really in use.
|
|
vrm_->assignVirt2Phys(cur->reg, physReg);
|
|
return;
|
|
}
|
|
|
|
backUpRegUses();
|
|
|
|
std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
|
|
SlotIndex StartPosition = cur->beginIndex();
|
|
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
|
|
|
|
// If start of this live interval is defined by a move instruction and its
|
|
// source is assigned a physical register that is compatible with the target
|
|
// register class, then we should try to assign it the same register.
|
|
// This can happen when the move is from a larger register class to a smaller
|
|
// one, e.g. X86::mov32to32_. These move instructions are not coalescable.
|
|
if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
|
|
VNInfo *vni = cur->begin()->valno;
|
|
if ((vni->def != SlotIndex()) && !vni->isUnused() &&
|
|
vni->isDefAccurate()) {
|
|
MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
|
|
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
|
|
if (CopyMI &&
|
|
tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
|
|
unsigned Reg = 0;
|
|
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
|
|
Reg = SrcReg;
|
|
else if (vrm_->isAssignedReg(SrcReg))
|
|
Reg = vrm_->getPhys(SrcReg);
|
|
if (Reg) {
|
|
if (SrcSubReg)
|
|
Reg = tri_->getSubReg(Reg, SrcSubReg);
|
|
if (DstSubReg)
|
|
Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
|
|
if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
|
|
mri_->setRegAllocationHint(cur->reg, 0, Reg);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// For every interval in inactive we overlap with, mark the
|
|
// register as not free and update spill weights.
|
|
for (IntervalPtrs::const_iterator i = inactive_.begin(),
|
|
e = inactive_.end(); i != e; ++i) {
|
|
unsigned Reg = i->first->reg;
|
|
assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
"Can only allocate virtual registers!");
|
|
const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
|
|
// If this is not in a related reg class to the register we're allocating,
|
|
// don't check it.
|
|
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
|
|
cur->overlapsFrom(*i->first, i->second-1)) {
|
|
Reg = vrm_->getPhys(Reg);
|
|
addRegUse(Reg);
|
|
SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
|
|
}
|
|
}
|
|
|
|
// Speculatively check to see if we can get a register right now. If not,
|
|
// we know we won't be able to by adding more constraints. If so, we can
|
|
// check to see if it is valid. Doing an exhaustive search of the fixed_ list
|
|
// is very bad (it contains all callee clobbered registers for any functions
|
|
// with a call), so we want to avoid doing that if possible.
|
|
unsigned physReg = getFreePhysReg(cur);
|
|
unsigned BestPhysReg = physReg;
|
|
if (physReg) {
|
|
// We got a register. However, if it's in the fixed_ list, we might
|
|
// conflict with it. Check to see if we conflict with it or any of its
|
|
// aliases.
|
|
SmallSet<unsigned, 8> RegAliases;
|
|
for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
|
|
RegAliases.insert(*AS);
|
|
|
|
bool ConflictsWithFixed = false;
|
|
for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
|
|
IntervalPtr &IP = fixed_[i];
|
|
if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
|
|
// Okay, this reg is on the fixed list. Check to see if we actually
|
|
// conflict.
|
|
LiveInterval *I = IP.first;
|
|
if (I->endIndex() > StartPosition) {
|
|
LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
|
|
IP.second = II;
|
|
if (II != I->begin() && II->start > StartPosition)
|
|
--II;
|
|
if (cur->overlapsFrom(*I, II)) {
|
|
ConflictsWithFixed = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Okay, the register picked by our speculative getFreePhysReg call turned
|
|
// out to be in use. Actually add all of the conflicting fixed registers to
|
|
// regUse_ so we can do an accurate query.
|
|
if (ConflictsWithFixed) {
|
|
// For every interval in fixed we overlap with, mark the register as not
|
|
// free and update spill weights.
|
|
for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
|
|
IntervalPtr &IP = fixed_[i];
|
|
LiveInterval *I = IP.first;
|
|
|
|
const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
|
|
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
|
|
I->endIndex() > StartPosition) {
|
|
LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
|
|
IP.second = II;
|
|
if (II != I->begin() && II->start > StartPosition)
|
|
--II;
|
|
if (cur->overlapsFrom(*I, II)) {
|
|
unsigned reg = I->reg;
|
|
addRegUse(reg);
|
|
SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
|
|
}
|
|
}
|
|
}
|
|
|
|
// Using the newly updated regUse_ object, which includes conflicts in the
|
|
// future, see if there are any registers available.
|
|
physReg = getFreePhysReg(cur);
|
|
}
|
|
}
|
|
|
|
// Restore the physical register tracker, removing information about the
|
|
// future.
|
|
restoreRegUses();
|
|
|
|
// If we find a free register, we are done: assign this virtual to
|
|
// the free physical register and add this interval to the active
|
|
// list.
|
|
if (physReg) {
|
|
DEBUG(dbgs() << tri_->getName(physReg) << '\n');
|
|
vrm_->assignVirt2Phys(cur->reg, physReg);
|
|
addRegUse(physReg);
|
|
active_.push_back(std::make_pair(cur, cur->begin()));
|
|
handled_.push_back(cur);
|
|
|
|
// "Upgrade" the physical register since it has been allocated.
|
|
UpgradeRegister(physReg);
|
|
if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
|
|
// "Downgrade" physReg to try to keep physReg from being allocated until
|
|
// the next reload from the same SS is allocated.
|
|
mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
|
|
DowngradeRegister(cur, physReg);
|
|
}
|
|
return;
|
|
}
|
|
DEBUG(dbgs() << "no free registers\n");
|
|
|
|
// Compile the spill weights into an array that is better for scanning.
|
|
std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
|
|
for (std::vector<std::pair<unsigned, float> >::iterator
|
|
I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
|
|
updateSpillWeights(SpillWeights, I->first, I->second, RC);
|
|
|
|
// for each interval in active, update spill weights.
|
|
for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
|
|
i != e; ++i) {
|
|
unsigned reg = i->first->reg;
|
|
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
|
|
"Can only allocate virtual registers!");
|
|
reg = vrm_->getPhys(reg);
|
|
updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
|
|
}
|
|
|
|
DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
|
|
|
|
// Find a register to spill.
|
|
float minWeight = HUGE_VALF;
|
|
unsigned minReg = 0;
|
|
|
|
bool Found = false;
|
|
std::vector<std::pair<unsigned,float> > RegsWeights;
|
|
if (!minReg || SpillWeights[minReg] == HUGE_VALF)
|
|
for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
|
|
e = RC->allocation_order_end(*mf_); i != e; ++i) {
|
|
unsigned reg = *i;
|
|
float regWeight = SpillWeights[reg];
|
|
// Skip recently allocated registers.
|
|
if (minWeight > regWeight && !isRecentlyUsed(reg))
|
|
Found = true;
|
|
RegsWeights.push_back(std::make_pair(reg, regWeight));
|
|
}
|
|
|
|
// If we didn't find a register that is spillable, try aliases?
|
|
if (!Found) {
|
|
for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
|
|
e = RC->allocation_order_end(*mf_); i != e; ++i) {
|
|
unsigned reg = *i;
|
|
// No need to worry about if the alias register size < regsize of RC.
|
|
// We are going to spill all registers that alias it anyway.
|
|
for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
|
|
RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
|
|
}
|
|
}
|
|
|
|
// Sort all potential spill candidates by weight.
|
|
std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
|
|
minReg = RegsWeights[0].first;
|
|
minWeight = RegsWeights[0].second;
|
|
if (minWeight == HUGE_VALF) {
|
|
// All registers must have inf weight. Just grab one!
|
|
minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
|
|
if (cur->weight == HUGE_VALF ||
|
|
li_->getApproximateInstructionCount(*cur) == 0) {
|
|
// Spill a physical register around defs and uses.
|
|
if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
|
|
// spillPhysRegAroundRegDefsUses may have invalidated iterator stored
|
|
// in fixed_. Reset them.
|
|
for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
|
|
IntervalPtr &IP = fixed_[i];
|
|
LiveInterval *I = IP.first;
|
|
if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
|
|
IP.second = I->advanceTo(I->begin(), StartPosition);
|
|
}
|
|
|
|
DowngradedRegs.clear();
|
|
assignRegOrStackSlotAtInterval(cur);
|
|
} else {
|
|
assert(false && "Ran out of registers during register allocation!");
|
|
llvm_report_error("Ran out of registers during register allocation!");
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
// Find up to 3 registers to consider as spill candidates.
|
|
unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
|
|
while (LastCandidate > 1) {
|
|
if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
|
|
break;
|
|
--LastCandidate;
|
|
}
|
|
|
|
DEBUG({
|
|
dbgs() << "\t\tregister(s) with min weight(s): ";
|
|
|
|
for (unsigned i = 0; i != LastCandidate; ++i)
|
|
dbgs() << tri_->getName(RegsWeights[i].first)
|
|
<< " (" << RegsWeights[i].second << ")\n";
|
|
});
|
|
|
|
// If the current has the minimum weight, we need to spill it and
|
|
// add any added intervals back to unhandled, and restart
|
|
// linearscan.
|
|
if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
|
|
DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
|
|
SmallVector<LiveInterval*, 8> spillIs;
|
|
std::vector<LiveInterval*> added;
|
|
|
|
added = spiller_->spill(cur, spillIs);
|
|
|
|
std::sort(added.begin(), added.end(), LISorter());
|
|
addStackInterval(cur, ls_, li_, mri_, *vrm_);
|
|
if (added.empty())
|
|
return; // Early exit if all spills were folded.
|
|
|
|
// Merge added with unhandled. Note that we have already sorted
|
|
// intervals returned by addIntervalsForSpills by their starting
|
|
// point.
|
|
// This also update the NextReloadMap. That is, it adds mapping from a
|
|
// register defined by a reload from SS to the next reload from SS in the
|
|
// same basic block.
|
|
MachineBasicBlock *LastReloadMBB = 0;
|
|
LiveInterval *LastReload = 0;
|
|
int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
|
|
for (unsigned i = 0, e = added.size(); i != e; ++i) {
|
|
LiveInterval *ReloadLi = added[i];
|
|
if (ReloadLi->weight == HUGE_VALF &&
|
|
li_->getApproximateInstructionCount(*ReloadLi) == 0) {
|
|
SlotIndex ReloadIdx = ReloadLi->beginIndex();
|
|
MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
|
|
int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
|
|
if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
|
|
// Last reload of same SS is in the same MBB. We want to try to
|
|
// allocate both reloads the same register and make sure the reg
|
|
// isn't clobbered in between if at all possible.
|
|
assert(LastReload->beginIndex() < ReloadIdx);
|
|
NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
|
|
}
|
|
LastReloadMBB = ReloadMBB;
|
|
LastReload = ReloadLi;
|
|
LastReloadSS = ReloadSS;
|
|
}
|
|
unhandled_.push(ReloadLi);
|
|
}
|
|
return;
|
|
}
|
|
|
|
++NumBacktracks;
|
|
|
|
// Push the current interval back to unhandled since we are going
|
|
// to re-run at least this iteration. Since we didn't modify it it
|
|
// should go back right in the front of the list
|
|
unhandled_.push(cur);
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
|
|
"did not choose a register to spill?");
|
|
|
|
// We spill all intervals aliasing the register with
|
|
// minimum weight, rollback to the interval with the earliest
|
|
// start point and let the linear scan algorithm run again
|
|
SmallVector<LiveInterval*, 8> spillIs;
|
|
|
|
// Determine which intervals have to be spilled.
|
|
findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
|
|
|
|
// Set of spilled vregs (used later to rollback properly)
|
|
SmallSet<unsigned, 8> spilled;
|
|
|
|
// The earliest start of a Spilled interval indicates up to where
|
|
// in handled we need to roll back
|
|
assert(!spillIs.empty() && "No spill intervals?");
|
|
SlotIndex earliestStart = spillIs[0]->beginIndex();
|
|
|
|
// Spill live intervals of virtual regs mapped to the physical register we
|
|
// want to clear (and its aliases). We only spill those that overlap with the
|
|
// current interval as the rest do not affect its allocation. we also keep
|
|
// track of the earliest start of all spilled live intervals since this will
|
|
// mark our rollback point.
|
|
std::vector<LiveInterval*> added;
|
|
while (!spillIs.empty()) {
|
|
LiveInterval *sli = spillIs.back();
|
|
spillIs.pop_back();
|
|
DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
|
|
if (sli->beginIndex() < earliestStart)
|
|
earliestStart = sli->beginIndex();
|
|
|
|
std::vector<LiveInterval*> newIs;
|
|
newIs = spiller_->spill(sli, spillIs, &earliestStart);
|
|
addStackInterval(sli, ls_, li_, mri_, *vrm_);
|
|
std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
|
|
spilled.insert(sli->reg);
|
|
}
|
|
|
|
DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
|
|
|
|
// Scan handled in reverse order up to the earliest start of a
|
|
// spilled live interval and undo each one, restoring the state of
|
|
// unhandled.
|
|
while (!handled_.empty()) {
|
|
LiveInterval* i = handled_.back();
|
|
// If this interval starts before t we are done.
|
|
if (!i->empty() && i->beginIndex() < earliestStart)
|
|
break;
|
|
DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
|
|
handled_.pop_back();
|
|
|
|
// When undoing a live interval allocation we must know if it is active or
|
|
// inactive to properly update regUse_ and the VirtRegMap.
|
|
IntervalPtrs::iterator it;
|
|
if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
|
|
active_.erase(it);
|
|
assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
|
|
if (!spilled.count(i->reg))
|
|
unhandled_.push(i);
|
|
delRegUse(vrm_->getPhys(i->reg));
|
|
vrm_->clearVirt(i->reg);
|
|
} else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
|
|
inactive_.erase(it);
|
|
assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
|
|
if (!spilled.count(i->reg))
|
|
unhandled_.push(i);
|
|
vrm_->clearVirt(i->reg);
|
|
} else {
|
|
assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
|
|
"Can only allocate virtual registers!");
|
|
vrm_->clearVirt(i->reg);
|
|
unhandled_.push(i);
|
|
}
|
|
|
|
DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
|
|
if (ii == DowngradeMap.end())
|
|
// It interval has a preference, it must be defined by a copy. Clear the
|
|
// preference now since the source interval allocation may have been
|
|
// undone as well.
|
|
mri_->setRegAllocationHint(i->reg, 0, 0);
|
|
else {
|
|
UpgradeRegister(ii->second);
|
|
}
|
|
}
|
|
|
|
// Rewind the iterators in the active, inactive, and fixed lists back to the
|
|
// point we reverted to.
|
|
RevertVectorIteratorsTo(active_, earliestStart);
|
|
RevertVectorIteratorsTo(inactive_, earliestStart);
|
|
RevertVectorIteratorsTo(fixed_, earliestStart);
|
|
|
|
// Scan the rest and undo each interval that expired after t and
|
|
// insert it in active (the next iteration of the algorithm will
|
|
// put it in inactive if required)
|
|
for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
|
|
LiveInterval *HI = handled_[i];
|
|
if (!HI->expiredAt(earliestStart) &&
|
|
HI->expiredAt(cur->beginIndex())) {
|
|
DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
|
|
active_.push_back(std::make_pair(HI, HI->begin()));
|
|
assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
|
|
addRegUse(vrm_->getPhys(HI->reg));
|
|
}
|
|
}
|
|
|
|
// Merge added with unhandled.
|
|
// This also update the NextReloadMap. That is, it adds mapping from a
|
|
// register defined by a reload from SS to the next reload from SS in the
|
|
// same basic block.
|
|
MachineBasicBlock *LastReloadMBB = 0;
|
|
LiveInterval *LastReload = 0;
|
|
int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
|
|
std::sort(added.begin(), added.end(), LISorter());
|
|
for (unsigned i = 0, e = added.size(); i != e; ++i) {
|
|
LiveInterval *ReloadLi = added[i];
|
|
if (ReloadLi->weight == HUGE_VALF &&
|
|
li_->getApproximateInstructionCount(*ReloadLi) == 0) {
|
|
SlotIndex ReloadIdx = ReloadLi->beginIndex();
|
|
MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
|
|
int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
|
|
if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
|
|
// Last reload of same SS is in the same MBB. We want to try to
|
|
// allocate both reloads the same register and make sure the reg
|
|
// isn't clobbered in between if at all possible.
|
|
assert(LastReload->beginIndex() < ReloadIdx);
|
|
NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
|
|
}
|
|
LastReloadMBB = ReloadMBB;
|
|
LastReload = ReloadLi;
|
|
LastReloadSS = ReloadSS;
|
|
}
|
|
unhandled_.push(ReloadLi);
|
|
}
|
|
}
|
|
|
|
unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
|
|
const TargetRegisterClass *RC,
|
|
unsigned MaxInactiveCount,
|
|
SmallVector<unsigned, 256> &inactiveCounts,
|
|
bool SkipDGRegs) {
|
|
unsigned FreeReg = 0;
|
|
unsigned FreeRegInactiveCount = 0;
|
|
|
|
std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
|
|
// Resolve second part of the hint (if possible) given the current allocation.
|
|
unsigned physReg = Hint.second;
|
|
if (physReg &&
|
|
TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
|
|
physReg = vrm_->getPhys(physReg);
|
|
|
|
TargetRegisterClass::iterator I, E;
|
|
tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
|
|
assert(I != E && "No allocatable register in this register class!");
|
|
|
|
// Scan for the first available register.
|
|
for (; I != E; ++I) {
|
|
unsigned Reg = *I;
|
|
// Ignore "downgraded" registers.
|
|
if (SkipDGRegs && DowngradedRegs.count(Reg))
|
|
continue;
|
|
// Skip recently allocated registers.
|
|
if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
|
|
FreeReg = Reg;
|
|
if (FreeReg < inactiveCounts.size())
|
|
FreeRegInactiveCount = inactiveCounts[FreeReg];
|
|
else
|
|
FreeRegInactiveCount = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If there are no free regs, or if this reg has the max inactive count,
|
|
// return this register.
|
|
if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
|
|
// Remember what register we picked so we can skip it next time.
|
|
if (FreeReg != 0) recordRecentlyUsed(FreeReg);
|
|
return FreeReg;
|
|
}
|
|
|
|
// Continue scanning the registers, looking for the one with the highest
|
|
// inactive count. Alkis found that this reduced register pressure very
|
|
// slightly on X86 (in rev 1.94 of this file), though this should probably be
|
|
// reevaluated now.
|
|
for (; I != E; ++I) {
|
|
unsigned Reg = *I;
|
|
// Ignore "downgraded" registers.
|
|
if (SkipDGRegs && DowngradedRegs.count(Reg))
|
|
continue;
|
|
if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
|
|
FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
|
|
FreeReg = Reg;
|
|
FreeRegInactiveCount = inactiveCounts[Reg];
|
|
if (FreeRegInactiveCount == MaxInactiveCount)
|
|
break; // We found the one with the max inactive count.
|
|
}
|
|
}
|
|
|
|
// Remember what register we picked so we can skip it next time.
|
|
recordRecentlyUsed(FreeReg);
|
|
|
|
return FreeReg;
|
|
}
|
|
|
|
/// getFreePhysReg - return a free physical register for this virtual register
|
|
/// interval if we have one, otherwise return 0.
|
|
unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
|
|
SmallVector<unsigned, 256> inactiveCounts;
|
|
unsigned MaxInactiveCount = 0;
|
|
|
|
const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
|
|
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
|
|
|
|
for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
|
|
i != e; ++i) {
|
|
unsigned reg = i->first->reg;
|
|
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
|
|
"Can only allocate virtual registers!");
|
|
|
|
// If this is not in a related reg class to the register we're allocating,
|
|
// don't check it.
|
|
const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
|
|
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
|
|
reg = vrm_->getPhys(reg);
|
|
if (inactiveCounts.size() <= reg)
|
|
inactiveCounts.resize(reg+1);
|
|
++inactiveCounts[reg];
|
|
MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
|
|
}
|
|
}
|
|
|
|
// If copy coalescer has assigned a "preferred" register, check if it's
|
|
// available first.
|
|
unsigned Preference = vrm_->getRegAllocPref(cur->reg);
|
|
if (Preference) {
|
|
DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
|
|
if (isRegAvail(Preference) &&
|
|
RC->contains(Preference))
|
|
return Preference;
|
|
}
|
|
|
|
if (!DowngradedRegs.empty()) {
|
|
unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
|
|
true);
|
|
if (FreeReg)
|
|
return FreeReg;
|
|
}
|
|
return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
|
|
}
|
|
|
|
FunctionPass* llvm::createLinearScanRegisterAllocator() {
|
|
return new RALinScan();
|
|
}
|