mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
402 lines
11 KiB
LLVM
402 lines
11 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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;
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; Floating-point scalar convert to signed integer (to nearest with ties to away)
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;
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define i32 @fcvtas_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtas_1w1s:
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;CHECK: fcvtas w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtas.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtas_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtas_1x1s:
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;CHECK: fcvtas x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtas.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtas_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtas_1w1d:
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;CHECK: fcvtas w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtas.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtas_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtas_1x1d:
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;CHECK: fcvtas x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtas.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtas.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtas.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtas.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtas.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to unsigned integer
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;
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define i32 @fcvtau_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtau_1w1s:
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;CHECK: fcvtau w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtau.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtau_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtau_1x1s:
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;CHECK: fcvtau x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtau.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtau_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtau_1w1d:
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;CHECK: fcvtau w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtau.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtau_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtau_1x1d:
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;CHECK: fcvtau x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtau.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtau.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtau.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtau.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtau.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to signed integer (toward -Inf)
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;
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define i32 @fcvtms_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtms_1w1s:
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;CHECK: fcvtms w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtms.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtms_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtms_1x1s:
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;CHECK: fcvtms x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtms.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtms_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtms_1w1d:
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;CHECK: fcvtms w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtms.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtms_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtms_1x1d:
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;CHECK: fcvtms x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtms.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtms.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtms.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtms.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtms.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to unsigned integer (toward -Inf)
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;
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define i32 @fcvtmu_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtmu_1w1s:
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;CHECK: fcvtmu w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtmu.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtmu_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtmu_1x1s:
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;CHECK: fcvtmu x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtmu.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtmu_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtmu_1w1d:
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;CHECK: fcvtmu w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtmu.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtmu_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtmu_1x1d:
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;CHECK: fcvtmu x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtmu.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtmu.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtmu.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtmu.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtmu.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to signed integer (to nearest with ties to even)
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;
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define i32 @fcvtns_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtns_1w1s:
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;CHECK: fcvtns w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtns.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtns_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtns_1x1s:
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;CHECK: fcvtns x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtns.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtns_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtns_1w1d:
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;CHECK: fcvtns w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtns.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtns_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtns_1x1d:
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;CHECK: fcvtns x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtns.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtns.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtns.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtns.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtns.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to unsigned integer (to nearest with ties to even)
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;
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define i32 @fcvtnu_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtnu_1w1s:
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;CHECK: fcvtnu w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtnu.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtnu_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtnu_1x1s:
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;CHECK: fcvtnu x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtnu.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtnu_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtnu_1w1d:
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;CHECK: fcvtnu w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtnu.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtnu_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtnu_1x1d:
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;CHECK: fcvtnu x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtnu.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtnu.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtnu.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtnu.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtnu.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to signed integer (toward +Inf)
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;
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define i32 @fcvtps_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtps_1w1s:
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;CHECK: fcvtps w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtps.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtps_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtps_1x1s:
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;CHECK: fcvtps x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtps.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtps_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtps_1w1d:
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;CHECK: fcvtps w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtps.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtps_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtps_1x1d:
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;CHECK: fcvtps x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtps.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtps.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtps.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtps.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtps.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to unsigned integer (toward +Inf)
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;
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define i32 @fcvtpu_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtpu_1w1s:
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;CHECK: fcvtpu w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtpu.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtpu_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtpu_1x1s:
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;CHECK: fcvtpu x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtpu.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtpu_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtpu_1w1d:
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;CHECK: fcvtpu w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtpu.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtpu_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtpu_1x1d:
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;CHECK: fcvtpu x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtpu.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtpu.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtpu.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtpu.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtpu.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to signed integer (toward zero)
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;
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define i32 @fcvtzs_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtzs_1w1s:
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;CHECK: fcvtzs w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtzs.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtzs_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtzs_1x1s:
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;CHECK: fcvtzs x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtzs.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtzs_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtzs_1w1d:
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;CHECK: fcvtzs w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtzs.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtzs_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtzs_1x1d:
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;CHECK: fcvtzs x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtzs.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtzs.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtzs.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtzs.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtzs.i64.f64(double) nounwind readnone
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;
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; Floating-point scalar convert to unsigned integer (toward zero)
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;
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define i32 @fcvtzu_1w1s(float %A) nounwind {
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;CHECK-LABEL: fcvtzu_1w1s:
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;CHECK: fcvtzu w0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtzu.i32.f32(float %A)
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ret i32 %tmp3
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}
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define i64 @fcvtzu_1x1s(float %A) nounwind {
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;CHECK-LABEL: fcvtzu_1x1s:
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;CHECK: fcvtzu x0, s0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtzu.i64.f32(float %A)
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ret i64 %tmp3
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}
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define i32 @fcvtzu_1w1d(double %A) nounwind {
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;CHECK-LABEL: fcvtzu_1w1d:
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;CHECK: fcvtzu w0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i32 @llvm.arm64.neon.fcvtzu.i32.f64(double %A)
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ret i32 %tmp3
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}
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define i64 @fcvtzu_1x1d(double %A) nounwind {
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;CHECK-LABEL: fcvtzu_1x1d:
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;CHECK: fcvtzu x0, d0
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;CHECK-NEXT: ret
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%tmp3 = call i64 @llvm.arm64.neon.fcvtzu.i64.f64(double %A)
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ret i64 %tmp3
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}
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declare i32 @llvm.arm64.neon.fcvtzu.i32.f32(float) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtzu.i64.f32(float) nounwind readnone
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declare i32 @llvm.arm64.neon.fcvtzu.i32.f64(double) nounwind readnone
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declare i64 @llvm.arm64.neon.fcvtzu.i64.f64(double) nounwind readnone
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