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https://github.com/c64scene-ar/llvm-6502.git
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4af58f145d
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8
16 lines
497 B
LLVM
16 lines
497 B
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
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@array = external global [0 x i32]
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define i64 @foo(i32 %i) {
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; CHECK: foo
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; CHECK: adrp x[[REG:[0-9]+]], _array@GOTPAGE
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; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _array@GOTPAGEOFF]
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; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
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; CHECK: ret
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds [0 x i32]* @array, i64 0, i64 %idxprom
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%tmp1 = load i32* %arrayidx, align 4
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%conv = sext i32 %tmp1 to i64
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ret i64 %conv
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}
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