llvm-6502/test/CodeGen/ARM64/fastcc-tailcall.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

25 lines
661 B
LLVM

; RUN: llc < %s -march=arm64 | FileCheck %s
define void @caller(i32* nocapture %p, i32 %a, i32 %b) nounwind optsize ssp {
; CHECK-NOT: stp
; CHECK: b {{_callee|callee}}
; CHECK-NOT: ldp
; CHECK: ret
%1 = icmp eq i32 %b, 0
br i1 %1, label %3, label %2
tail call fastcc void @callee(i32* %p, i32 %a) optsize
br label %3
ret void
}
define internal fastcc void @callee(i32* nocapture %p, i32 %a) nounwind optsize noinline ssp {
store volatile i32 %a, i32* %p, align 4, !tbaa !0
ret void
}
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}