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https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.6 KiB
LLVM
37 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
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; rdar://13214163 - Make sure we generate a correct lookup table for the TBL
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; instruction when the element size of the vector is not 8 bits. We were
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; getting both the endianness wrong and the element indexing wrong.
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define <8 x i16> @foo(<8 x i16> %a) nounwind readnone {
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; CHECK: .section __TEXT,__literal16,16byte_literals
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; CHECK: .align 4
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; CHECK:lCPI0_0:
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 1 ; 0x1
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 1 ; 0x1
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 1 ; 0x1
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 1 ; 0x1
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; CHECK: .byte 8 ; 0x8
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; CHECK: .byte 9 ; 0x9
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; CHECK: .byte 8 ; 0x8
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; CHECK: .byte 9 ; 0x9
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; CHECK: .byte 8 ; 0x8
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; CHECK: .byte 9 ; 0x9
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; CHECK: .byte 8 ; 0x8
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; CHECK: .byte 9 ; 0x9
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; CHECK: .section __TEXT,__text,regular,pure_instructions
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; CHECK: .globl _foo
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; CHECK: .align 2
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; CHECK:_foo: ; @foo
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; CHECK: adrp [[BASE:x[0-9]+]], lCPI0_0@PAGE
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; CHECK: ldr q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0@PAGEOFF]
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; CHECK: tbl.16b v0, { v0 }, v[[REG]]
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; CHECK: ret
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%val = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
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ret <8 x i16> %val
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}
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