mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0a088b1fc5
In all cases, if a "mov" alias exists, it is the canonical form of the instruction. Now that TableGen can support aliases containing syntax variants, we can enable them and improve the quality of the asm output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208874 91177308-0d34-0410-b5e6-96231b3b80d8
237 lines
7.4 KiB
LLVM
237 lines
7.4 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define void @fcmltz_4s(<4 x float> %a, <4 x i16>* %p) nounwind {
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;CHECK-LABEL: fcmltz_4s:
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;CHECK: fcmlt.4s [[REG:v[0-9]+]], v0, #0
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;CHECK-NEXT: xtn.4h v[[REG_1:[0-9]+]], [[REG]]
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;CHECK-NEXT: str d[[REG_1]], [x0]
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;CHECK-NEXT: ret
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%tmp = fcmp olt <4 x float> %a, zeroinitializer
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%tmp2 = sext <4 x i1> %tmp to <4 x i16>
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store <4 x i16> %tmp2, <4 x i16>* %p, align 8
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ret void
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}
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define <2 x i32> @facge_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: facge_2s:
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;CHECK: facge.2s
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = call <2 x i32> @llvm.arm64.neon.facge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @facge_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: facge_4s:
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;CHECK: facge.4s
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = call <4 x i32> @llvm.arm64.neon.facge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @facge_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
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;CHECK-LABEL: facge_2d:
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;CHECK: facge.2d
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%tmp1 = load <2 x double>* %A
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%tmp2 = load <2 x double>* %B
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%tmp3 = call <2 x i64> @llvm.arm64.neon.facge.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <2 x i32> @llvm.arm64.neon.facge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm64.neon.facge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x i64> @llvm.arm64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone
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define <2 x i32> @facgt_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: facgt_2s:
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;CHECK: facgt.2s
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = call <2 x i32> @llvm.arm64.neon.facgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @facgt_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: facgt_4s:
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;CHECK: facgt.4s
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = call <4 x i32> @llvm.arm64.neon.facgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @facgt_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
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;CHECK-LABEL: facgt_2d:
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;CHECK: facgt.2d
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%tmp1 = load <2 x double>* %A
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%tmp2 = load <2 x double>* %B
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%tmp3 = call <2 x i64> @llvm.arm64.neon.facgt.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <2 x i32> @llvm.arm64.neon.facgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm64.neon.facgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x i64> @llvm.arm64.neon.facgt.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone
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define i32 @facge_s(float %A, float %B) nounwind {
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; CHECK-LABEL: facge_s:
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; CHECK: facge {{s[0-9]+}}, s0, s1
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%mask = call i32 @llvm.arm64.neon.facge.i32.f32(float %A, float %B)
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ret i32 %mask
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}
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define i64 @facge_d(double %A, double %B) nounwind {
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; CHECK-LABEL: facge_d:
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; CHECK: facge {{d[0-9]+}}, d0, d1
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%mask = call i64 @llvm.arm64.neon.facge.i64.f64(double %A, double %B)
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ret i64 %mask
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}
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declare i64 @llvm.arm64.neon.facge.i64.f64(double, double)
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declare i32 @llvm.arm64.neon.facge.i32.f32(float, float)
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define i32 @facgt_s(float %A, float %B) nounwind {
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; CHECK-LABEL: facgt_s:
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; CHECK: facgt {{s[0-9]+}}, s0, s1
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%mask = call i32 @llvm.arm64.neon.facgt.i32.f32(float %A, float %B)
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ret i32 %mask
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}
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define i64 @facgt_d(double %A, double %B) nounwind {
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; CHECK-LABEL: facgt_d:
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; CHECK: facgt {{d[0-9]+}}, d0, d1
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%mask = call i64 @llvm.arm64.neon.facgt.i64.f64(double %A, double %B)
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ret i64 %mask
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}
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declare i64 @llvm.arm64.neon.facgt.i64.f64(double, double)
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declare i32 @llvm.arm64.neon.facgt.i32.f32(float, float)
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define <8 x i8> @cmtst_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: cmtst_8b:
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;CHECK: cmtst.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%commonbits = and <8 x i8> %tmp1, %tmp2
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%mask = icmp ne <8 x i8> %commonbits, zeroinitializer
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%res = sext <8 x i1> %mask to <8 x i8>
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ret <8 x i8> %res
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}
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define <16 x i8> @cmtst_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: cmtst_16b:
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;CHECK: cmtst.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%commonbits = and <16 x i8> %tmp1, %tmp2
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%mask = icmp ne <16 x i8> %commonbits, zeroinitializer
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%res = sext <16 x i1> %mask to <16 x i8>
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ret <16 x i8> %res
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}
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define <4 x i16> @cmtst_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: cmtst_4h:
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;CHECK: cmtst.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%commonbits = and <4 x i16> %tmp1, %tmp2
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%mask = icmp ne <4 x i16> %commonbits, zeroinitializer
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%res = sext <4 x i1> %mask to <4 x i16>
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ret <4 x i16> %res
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}
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define <8 x i16> @cmtst_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: cmtst_8h:
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;CHECK: cmtst.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%commonbits = and <8 x i16> %tmp1, %tmp2
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%mask = icmp ne <8 x i16> %commonbits, zeroinitializer
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%res = sext <8 x i1> %mask to <8 x i16>
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ret <8 x i16> %res
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}
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define <2 x i32> @cmtst_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: cmtst_2s:
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;CHECK: cmtst.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%commonbits = and <2 x i32> %tmp1, %tmp2
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%mask = icmp ne <2 x i32> %commonbits, zeroinitializer
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%res = sext <2 x i1> %mask to <2 x i32>
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ret <2 x i32> %res
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}
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define <4 x i32> @cmtst_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: cmtst_4s:
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;CHECK: cmtst.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%commonbits = and <4 x i32> %tmp1, %tmp2
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%mask = icmp ne <4 x i32> %commonbits, zeroinitializer
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%res = sext <4 x i1> %mask to <4 x i32>
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ret <4 x i32> %res
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}
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define <2 x i64> @cmtst_2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: cmtst_2d:
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;CHECK: cmtst.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%commonbits = and <2 x i64> %tmp1, %tmp2
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%mask = icmp ne <2 x i64> %commonbits, zeroinitializer
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%res = sext <2 x i1> %mask to <2 x i64>
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ret <2 x i64> %res
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}
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define <1 x i64> @fcmeq_d(<1 x double> %A, <1 x double> %B) nounwind {
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; CHECK-LABEL: fcmeq_d:
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; CHECK: fcmeq {{d[0-9]+}}, d0, d1
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%tst = fcmp oeq <1 x double> %A, %B
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%mask = sext <1 x i1> %tst to <1 x i64>
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ret <1 x i64> %mask
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}
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define <1 x i64> @fcmge_d(<1 x double> %A, <1 x double> %B) nounwind {
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; CHECK-LABEL: fcmge_d:
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; CHECK: fcmge {{d[0-9]+}}, d0, d1
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%tst = fcmp oge <1 x double> %A, %B
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%mask = sext <1 x i1> %tst to <1 x i64>
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ret <1 x i64> %mask
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}
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define <1 x i64> @fcmle_d(<1 x double> %A, <1 x double> %B) nounwind {
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; CHECK-LABEL: fcmle_d:
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; CHECK: fcmge {{d[0-9]+}}, d1, d0
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%tst = fcmp ole <1 x double> %A, %B
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%mask = sext <1 x i1> %tst to <1 x i64>
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ret <1 x i64> %mask
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}
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define <1 x i64> @fcmgt_d(<1 x double> %A, <1 x double> %B) nounwind {
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; CHECK-LABEL: fcmgt_d:
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; CHECK: fcmgt {{d[0-9]+}}, d0, d1
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%tst = fcmp ogt <1 x double> %A, %B
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%mask = sext <1 x i1> %tst to <1 x i64>
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ret <1 x i64> %mask
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}
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define <1 x i64> @fcmlt_d(<1 x double> %A, <1 x double> %B) nounwind {
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; CHECK-LABEL: fcmlt_d:
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; CHECK: fcmgt {{d[0-9]+}}, d1, d0
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%tst = fcmp olt <1 x double> %A, %B
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%mask = sext <1 x i1> %tst to <1 x i64>
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ret <1 x i64> %mask
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}
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define <1 x i64> @cmnez_d(<1 x i64> %A) nounwind {
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; CHECK-LABEL: cmnez_d:
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; CHECK: cmeq d[[EQ:[0-9]+]], d0, #0
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; CHECK: mvn.8b v0, v[[EQ]]
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%tst = icmp ne <1 x i64> %A, zeroinitializer
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%mask = sext <1 x i1> %tst to <1 x i64>
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ret <1 x i64> %mask
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}
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