mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
814 B
LLVM
35 lines
814 B
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
|
|
|
|
define <2 x i32> @c1(<2 x float> %a) nounwind readnone ssp {
|
|
; CHECK: c1
|
|
; CHECK: fcvtzs.2s v0, v0
|
|
; CHECK: ret
|
|
%vcvt.i = fptosi <2 x float> %a to <2 x i32>
|
|
ret <2 x i32> %vcvt.i
|
|
}
|
|
|
|
define <2 x i32> @c2(<2 x float> %a) nounwind readnone ssp {
|
|
; CHECK: c2
|
|
; CHECK: fcvtzu.2s v0, v0
|
|
; CHECK: ret
|
|
%vcvt.i = fptoui <2 x float> %a to <2 x i32>
|
|
ret <2 x i32> %vcvt.i
|
|
}
|
|
|
|
define <4 x i32> @c3(<4 x float> %a) nounwind readnone ssp {
|
|
; CHECK: c3
|
|
; CHECK: fcvtzs.4s v0, v0
|
|
; CHECK: ret
|
|
%vcvt.i = fptosi <4 x float> %a to <4 x i32>
|
|
ret <4 x i32> %vcvt.i
|
|
}
|
|
|
|
define <4 x i32> @c4(<4 x float> %a) nounwind readnone ssp {
|
|
; CHECK: c4
|
|
; CHECK: fcvtzu.4s v0, v0
|
|
; CHECK: ret
|
|
%vcvt.i = fptoui <4 x float> %a to <4 x i32>
|
|
ret <4 x i32> %vcvt.i
|
|
}
|
|
|