mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
999 B
LLVM
41 lines
999 B
LLVM
; RUN: llc -march=arm64 < %s | FileCheck %s
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@var32 = global i32 0
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define void @test_zextloadi1_unscaled(i1* %base) {
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; CHECK-LABEL: test_zextloadi1_unscaled:
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; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
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%addr = getelementptr i1* %base, i32 -7
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%val = load i1* %addr, align 1
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%extended = zext i1 %val to i32
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store i32 %extended, i32* @var32, align 4
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ret void
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}
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define void @test_zextloadi8_unscaled(i8* %base) {
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; CHECK-LABEL: test_zextloadi8_unscaled:
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; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
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%addr = getelementptr i8* %base, i32 -7
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%val = load i8* %addr, align 1
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%extended = zext i8 %val to i32
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store i32 %extended, i32* @var32, align 4
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ret void
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}
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define void @test_zextloadi16_unscaled(i16* %base) {
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; CHECK-LABEL: test_zextloadi16_unscaled:
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; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-14]
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%addr = getelementptr i16* %base, i32 -7
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%val = load i16* %addr, align 2
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%extended = zext i16 %val to i32
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store i32 %extended, i32* @var32, align 4
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ret void
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}
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