Juergen Ributzka 301d3d04f0 [FastISel][AArch64] Teach the address computation code to also fold sign-/zero-extends. ...

The code already folds sign-/zero-extends, but only if they are arguments to
mul and shift instructions. This extends the code to also fold them when they
are direct inputs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219187 91177308-0d34-0410-b5e6-96231b3b80d8

2014-10-07 03:40:06 +00:00

..

AsmParser

AArch64: allow constant expressions for shifted reg literals

2014-09-23 22:16:02 +00:00

Disassembler

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

InstPrinter

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

MCTargetDesc

Fix segfault in AArch64 backend with -g and -mbig-endian

2014-09-23 15:38:11 +00:00

TargetInfo

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Utils

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

AArch64.h

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AArch64.td

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AArch64A57FPLoadBalancing.cpp

Eliminate some deep std::vector copies. NFC.

2014-10-03 18:33:16 +00:00

AArch64AddressTypePromotion.cpp

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AArch64AdvSIMDScalarPass.cpp

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AArch64AsmPrinter.cpp

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AArch64BranchRelaxation.cpp

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AArch64CallingConvention.td

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AArch64CleanupLocalDynamicTLSPass.cpp

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AArch64CollectLOH.cpp

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AArch64ConditionalCompares.cpp

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AArch64ConditionOptimizer.cpp

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AArch64DeadRegisterDefinitionsPass.cpp

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AArch64ExpandPseudoInsts.cpp

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AArch64FastISel.cpp

[FastISel][AArch64] Teach the address computation code to also fold sign-/zero-extends.

2014-10-07 03:40:06 +00:00

AArch64FrameLowering.cpp

[Stackmaps] Make ithe frame-pointer required for stackmaps.

2014-10-02 22:21:49 +00:00

AArch64FrameLowering.h

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AArch64InstrAtomics.td

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AArch64InstrFormats.td

[AArch64] Allow access to all system registers with MRS/MSR instructions.

2014-10-01 10:13:59 +00:00

AArch64InstrInfo.cpp

Move the complex address expression out of DIVariable and into an extra

2014-10-01 18:55:02 +00:00

AArch64InstrInfo.h

Move the complex address expression out of DIVariable and into an extra

2014-10-01 18:55:02 +00:00

AArch64InstrInfo.td

Add missing natual vector cast.

2014-10-01 09:59:45 +00:00

AArch64ISelDAGToDAG.cpp

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AArch64ISelLowering.cpp

Make AAMDNodes ctor and operator bool (!!!) explicit, mop up bugs and weirdness exposed by it.

2014-10-04 22:44:29 +00:00

AArch64ISelLowering.h

constify TargetMachine parameter.

2014-10-03 00:42:41 +00:00

AArch64LoadStoreOptimizer.cpp

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AArch64MachineCombinerPattern.h

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AArch64MachineFunctionInfo.h

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AArch64MCInstLower.cpp

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AArch64MCInstLower.h

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AArch64PBQPRegAlloc.cpp

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AArch64PerfectShuffle.h

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AArch64PromoteConstant.cpp

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AArch64RegisterInfo.cpp

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AArch64RegisterInfo.h

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AArch64RegisterInfo.td

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AArch64SchedA53.td

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AArch64SchedA57.td

[AArch64] Refines the Cortex-A57 Machine Model

2014-09-29 21:27:36 +00:00

AArch64SchedA57WriteRes.td

[AArch64] Refines the Cortex-A57 Machine Model

2014-09-29 21:27:36 +00:00

AArch64SchedCyclone.td

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AArch64Schedule.td

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AArch64SelectionDAGInfo.cpp

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AArch64SelectionDAGInfo.h

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AArch64StorePairSuppress.cpp

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AArch64Subtarget.cpp

constify TargetMachine parameter.

2014-10-03 00:42:41 +00:00

AArch64Subtarget.h

constify TargetMachine parameter.

2014-10-03 00:42:41 +00:00

AArch64TargetMachine.cpp

Add subtarget caches to aarch64, arm, ppc, and x86.

2014-10-06 06:45:36 +00:00

AArch64TargetMachine.h

Add subtarget caches to aarch64, arm, ppc, and x86.

2014-10-06 06:45:36 +00:00

AArch64TargetObjectFile.cpp

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AArch64TargetObjectFile.h

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AArch64TargetTransformInfo.cpp

[AArch64] Improve cost model to handle sdiv by a pow-of-two.

2014-09-29 13:59:31 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

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