llvm-6502/test/CodeGen/ARM
Rafael Espindola 5f450d2948 add more condition codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-02 20:24:25 +00:00
..
argaddr.ll add a "load effective address" 2006-08-17 17:09:40 +00:00
branch.ll add more condition codes 2006-09-02 20:24:25 +00:00
call.ll implement function calling of functions with up to 4 arguments 2006-07-25 20:17:20 +00:00
dg.exp create test/Regression/CodeGen/ARM/ and add a minimal test to it 2006-05-25 10:49:19 +00:00
hello.ll use a 'register pressure reducing' scheduler 2006-08-04 12:48:42 +00:00
ldr.ll select code like 2006-08-14 19:01:24 +00:00
ret0.ll create test/Regression/CodeGen/ARM/ and add a minimal test to it 2006-05-25 10:49:19 +00:00
ret_arg1.ll added some tests for argument passing 2006-06-01 22:01:25 +00:00
ret_arg2.ll added some tests for argument passing 2006-06-01 22:01:25 +00:00
ret_arg3.ll added some tests for argument passing 2006-06-01 22:01:25 +00:00
ret_arg4.ll added some tests for argument passing 2006-06-01 22:01:25 +00:00
ret_arg5.ll initial implementation of ARMRegisterInfo::eliminateFrameIndex 2006-06-18 00:08:07 +00:00
ret_void.ll added some tests for argument passing 2006-06-01 22:01:25 +00:00
select.ll run llc with -march=arm in select.ll 2006-08-22 16:19:54 +00:00
vargs2.ll test case for varargs functions 2006-08-25 17:57:36 +00:00
vargs.ll fix the spill code 2006-08-09 16:41:12 +00:00