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https://github.com/c64scene-ar/llvm-6502.git
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f09378397e
per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233411 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
3.3 KiB
C++
117 lines
3.3 KiB
C++
//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints a Mips MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H
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#define LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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// These enumeration declarations were originally in MipsInstrInfo.h but
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// had to be moved here to avoid circular dependencies between
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// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
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namespace Mips {
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// Mips Branch Codes
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enum FPBranchCode {
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BRANCH_F,
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BRANCH_T,
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BRANCH_FL,
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BRANCH_TL,
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BRANCH_INVALID
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};
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// Mips Condition Codes
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enum CondCode {
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// To be used with float branch True
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FCOND_F,
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FCOND_UN,
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FCOND_OEQ,
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FCOND_UEQ,
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FCOND_OLT,
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FCOND_ULT,
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FCOND_OLE,
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FCOND_ULE,
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FCOND_SF,
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FCOND_NGLE,
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FCOND_SEQ,
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FCOND_NGL,
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FCOND_LT,
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FCOND_NGE,
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FCOND_LE,
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FCOND_NGT,
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// To be used with float branch False
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// This conditions have the same mnemonic as the
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// above ones, but are used with a branch False;
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FCOND_T,
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FCOND_OR,
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FCOND_UNE,
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FCOND_ONE,
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FCOND_UGE,
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FCOND_OGE,
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FCOND_UGT,
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FCOND_OGT,
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FCOND_ST,
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FCOND_GLE,
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FCOND_SNE,
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FCOND_GL,
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FCOND_NLT,
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FCOND_GE,
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FCOND_NLE,
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FCOND_GT
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};
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const char *MipsFCCToString(Mips::CondCode CC);
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} // end namespace Mips
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class TargetMachine;
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class MipsInstPrinter : public MCInstPrinter {
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public:
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MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI)
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: MCInstPrinter(MAI, MII, MRI) {}
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
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const MCSubtargetInfo &STI) override;
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bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
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void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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unsigned PrintMethodIdx, raw_ostream &O);
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private:
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O);
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void printUnsignedImm8(const MCInst *MI, int opNum, raw_ostream &O);
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void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
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void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
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void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
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void printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O);
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void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
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bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
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raw_ostream &OS);
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bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
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unsigned OpNo1, raw_ostream &OS);
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bool printAlias(const MCInst &MI, raw_ostream &OS);
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void printSaveRestore(const MCInst *MI, raw_ostream &O);
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void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O);
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};
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} // end namespace llvm
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#endif
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