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159b6f1775
These tests are failing on Haswell CPUs due to different instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188908 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.5 KiB
LLVM
47 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
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; PR1198
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define i64 @foo(i64 %x, i64 %y) {
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%tmp0 = zext i64 %x to i128
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%tmp1 = zext i64 %y to i128
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%tmp2 = mul i128 %tmp0, %tmp1
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%tmp7 = zext i32 64 to i128
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%tmp3 = lshr i128 %tmp2, %tmp7
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%tmp4 = trunc i128 %tmp3 to i64
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ret i64 %tmp4
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}
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; <rdar://problem/14096009> superfluous multiply by high part of
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; zero-extended value.
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; CHECK: @mul1
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; CHECK-NOT: imulq
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; CHECK: mulq
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; CHECK-NOT: imulq
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define i64 @mul1(i64 %n, i64* nocapture %z, i64* nocapture %x, i64 %y) {
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entry:
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%conv = zext i64 %y to i128
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%cmp11 = icmp eq i64 %n, 0
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br i1 %cmp11, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body
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%carry.013 = phi i64 [ %conv6, %for.body ], [ 0, %entry ]
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%i.012 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i64* %x, i64 %i.012
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%0 = load i64* %arrayidx, align 8
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%conv2 = zext i64 %0 to i128
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%mul = mul i128 %conv2, %conv
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%conv3 = zext i64 %carry.013 to i128
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%add = add i128 %mul, %conv3
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%conv4 = trunc i128 %add to i64
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%arrayidx5 = getelementptr inbounds i64* %z, i64 %i.012
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store i64 %conv4, i64* %arrayidx5, align 8
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%shr = lshr i128 %add, 64
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%conv6 = trunc i128 %shr to i64
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%inc = add i64 %i.012, 1
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%exitcond = icmp eq i64 %inc, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret i64 0
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}
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