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6520e20e4f
and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
3.6 KiB
C++
109 lines
3.6 KiB
C++
//===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Alpha uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
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#define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "Alpha.h"
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namespace llvm {
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namespace AlphaISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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//These corrospond to the identical Instruction
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CVTQT_, CVTQS_, CVTTQ_,
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/// GPRelHi/GPRelLo - These represent the high and low 16-bit
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/// parts of a global address respectively.
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GPRelHi, GPRelLo,
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/// RetLit - Literal Relocation of a Global
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RelLit,
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/// GlobalRetAddr - used to restore the return address
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GlobalRetAddr,
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/// CALL - Normal call.
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CALL,
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/// DIVCALL - used for special library calls for div and rem
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DivCall,
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/// return flag operand
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RET_FLAG,
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/// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
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/// corresponds to the COND_BRANCH pseudo instruction.
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/// *PRC is the input register to compare to zero,
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/// OPC is the branch opcode to use (e.g. Alpha::BEQ),
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/// DESTBB is the destination block to branch to, and INFLAG is
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/// an optional input flag argument.
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COND_BRANCH_I, COND_BRANCH_F
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};
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}
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class AlphaTargetLowering : public TargetLowering {
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int VarArgsOffset; // What is the offset to the first vaarg
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int VarArgsBase; // What is the base FrameIndex
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bool useITOF;
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public:
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explicit AlphaTargetLowering(TargetMachine &TM);
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/// getSetCCResultType - Get the SETCC result ValueType
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virtual MVT getSetCCResultType(const SDValue &) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
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// Friendly names for dumps
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const char *getTargetNodeName(unsigned Opcode) const;
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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virtual std::pair<SDValue, SDValue>
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LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
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bool isVarArg, bool isInreg, unsigned CC, bool isTailCall,
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SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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bool hasITOF() { return useITOF; }
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MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB);
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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private:
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// Helpers for custom lowering.
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void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
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SelectionDAG &DAG);
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};
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}
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#endif // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
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