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f6713916fb
Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
17 lines
435 B
LLVM
17 lines
435 B
LLVM
; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=linearscan | FileCheck %s
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; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=basic | FileCheck %s
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; The greedy register allocator uses a single CSR here, invalidating the test.
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@b = external global i64*
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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; CHECK: push {lr}
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; CHECK: pop {lr}
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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%2 = mul i64 %1, %a
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ret i64 %2
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}
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