mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b48783b091
base point of a load, and the overall alignment of the load. This caused infinite loops in DAG combine with the original application of this patch. ORIGINAL COMMIT LOG: When the target-independent DAGCombiner inferred a higher alignment for a load, it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174431 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.0 KiB
LLVM
95 lines
2.0 KiB
LLVM
; RUN: llc < %s -mcpu=generic -mtriple=i686-pc-linux-gnu -asm-verbose=0 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
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target triple = "i686-pc-linux-gnu"
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define zeroext i16 @test1(i16 zeroext %x) nounwind {
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entry:
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%div = udiv i16 %x, 33
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ret i16 %div
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; CHECK: test1:
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; CHECK: imull $63551, %eax, %eax
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; CHECK-NEXT: shrl $21, %eax
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; CHECK-NEXT: ret
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}
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define zeroext i16 @test2(i8 signext %x, i16 zeroext %c) nounwind readnone ssp noredzone {
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entry:
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%div = udiv i16 %c, 3
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ret i16 %div
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; CHECK: test2:
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; CHECK: imull $43691, %eax, %eax
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; CHECK-NEXT: shrl $17, %eax
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; CHECK-NEXT: ret
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}
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define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) nounwind readnone ssp noredzone {
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entry:
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%div = udiv i8 %c, 3
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ret i8 %div
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; CHECK: test3:
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; CHECK: movzbl 8(%esp), %eax
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; CHECK-NEXT: imull $171, %eax, %eax
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; CHECK-NEXT: shrl $9, %eax
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; CHECK-NEXT: ret
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}
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define signext i16 @test4(i16 signext %x) nounwind {
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entry:
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%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
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ret i16 %div
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; CHECK: test4:
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; CHECK: imull $1986, %eax, %
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}
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define i32 @test5(i32 %A) nounwind {
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%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
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ret i32 %tmp1
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; CHECK: test5:
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; CHECK: movl $365384439, %eax
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; CHECK: mull 4(%esp)
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}
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define signext i16 @test6(i16 signext %x) nounwind {
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entry:
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%div = sdiv i16 %x, 10
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ret i16 %div
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; CHECK: test6:
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; CHECK: imull $26215, %eax, %ecx
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; CHECK: sarl $18, %ecx
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; CHECK: shrl $15, %eax
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}
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define i32 @test7(i32 %x) nounwind {
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%div = udiv i32 %x, 28
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ret i32 %div
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; CHECK: test7:
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; CHECK: shrl $2
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; CHECK: movl $613566757
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; CHECK: mull
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; CHECK-NOT: shrl
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; CHECK: ret
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}
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; PR13326
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define i8 @test8(i8 %x) nounwind {
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%div = udiv i8 %x, 78
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ret i8 %div
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; CHECK: test8:
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; CHECK: shrb %
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; CHECK: imull $211
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; CHECK: shrl $13
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; CHECK: ret
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}
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define i8 @test9(i8 %x) nounwind {
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%div = udiv i8 %x, 116
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ret i8 %div
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; CHECK: test9:
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; CHECK: shrb $2
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; CHECK: imull $71
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; CHECK: shrl $11
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; CHECK: ret
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}
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