Ahmed Bougacha 23ed37a6b7 Make SubRegIndex size mandatory, following r183020. ... This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-31 23:45:26 +00:00
..
CostTable.h	Moving Cost Tables up to share with other targets	2013-01-24 23:01:00 +00:00
Mangler.h	Don't reach into the middle of TargetMachine and cache one of its ivars.	2013-05-29 20:37:19 +00:00
Target.td	Make SubRegIndex size mandatory, following r183020.	2013-05-31 23:45:26 +00:00
TargetCallingConv.h	Remove unused, undefined ArgFlagsTy::getArgFlagsString; add a comment about 'returned'	2013-04-21 18:05:20 +00:00
TargetCallingConv.td
TargetFrameLowering.h	Provide the register scavenger to processFunctionBeforeFrameFinalized	2013-03-14 20:33:40 +00:00
TargetInstrInfo.h	Add a comment to TargetInstrInfo about FoldImmediate	2013-04-06 19:30:20 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td
TargetJITInfo.h
TargetLibraryInfo.h	Convert sqrt functions into sqrt instructions when -ffast-math is in effect.	2013-05-27 15:44:35 +00:00
TargetLowering.h	Loop Strength Reduce: Scaling factor cost.	2013-05-31 21:29:03 +00:00
TargetLoweringObjectFile.h
TargetMachine.h	Remove the MachineMove class.	2013-05-13 01:16:13 +00:00
TargetOpcodes.h
TargetOptions.h	Remove exception handling support from the old JIT.	2013-05-07 20:53:59 +00:00
TargetRegisterInfo.h	Add TargetRegisterInfo::getCoveringLanes().	2013-05-16 18:03:08 +00:00
TargetSchedule.td	MachineModel: Add a ProcResGroup class.	2013-03-14 21:21:50 +00:00
TargetSelectionDAG.td	Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.	2013-05-22 06:36:09 +00:00
TargetSelectionDAGInfo.h	Track IR ordering of SelectionDAG nodes 2/4.	2013-05-25 02:42:55 +00:00
TargetSubtargetInfo.h	Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.	2013-02-15 22:31:27 +00:00