Adam Nemet adf1668bec [ARM64] PR19792: Fix cycle in DAG after performPostLD1Combine ... Povray and dealII currently assert with "Overran sorted position" in AssignTopologicalOrder. The problem is that performPostLD1Combine can introduce cycles. Consider: (insert_vector_elt (INSERT_SUBREG undef, (load (add %vreg0, Constant<8>), undef), <= A TargetConstant<2>), (load %vreg0, undef), <= B Constant<1>) This is turned into a LD1LANEpost node. However the address in A is not a valid user of the post-incremented address of B in LD1LANEpost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209242 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-20 21:47:07 +00:00
..
AsmParser	[ARM64] Split tbz/tbnz into W/X register variant	2014-05-19 15:58:15 +00:00
Disassembler	[ARM64] Split tbz/tbnz into W/X register variant	2014-05-19 15:58:15 +00:00
InstPrinter	[ARM64] Split tbz/tbnz into W/X register variant	2014-05-19 15:58:15 +00:00
MCTargetDesc
TargetInfo
Utils
ARM64.h
ARM64.td
ARM64AddressTypePromotion.cpp
ARM64AdvSIMDScalarPass.cpp
ARM64AsmPrinter.cpp
ARM64BranchRelaxation.cpp	[ARM64] Split tbz/tbnz into W/X register variant	2014-05-19 15:58:15 +00:00
ARM64CallingConv.h
ARM64CallingConvention.td
ARM64CleanupLocalDynamicTLSPass.cpp
ARM64CollectLOH.cpp
ARM64ConditionalCompares.cpp
ARM64DeadRegisterDefinitionsPass.cpp
ARM64ExpandPseudoInsts.cpp
ARM64FastISel.cpp
ARM64FrameLowering.cpp
ARM64FrameLowering.h
ARM64InstrAtomics.td
ARM64InstrFormats.td	TableGen: convert InstAlias's Emit bit to an int.	2014-05-20 09:17:16 +00:00
ARM64InstrInfo.cpp	[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.	2014-05-19 22:59:51 +00:00
ARM64InstrInfo.h	[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.	2014-05-19 22:59:51 +00:00
ARM64InstrInfo.td	TableGen: convert InstAlias's Emit bit to an int.	2014-05-20 09:17:16 +00:00
ARM64ISelDAGToDAG.cpp
ARM64ISelLowering.cpp	[ARM64] PR19792: Fix cycle in DAG after performPostLD1Combine	2014-05-20 21:47:07 +00:00
ARM64ISelLowering.h
ARM64LoadStoreOptimizer.cpp
ARM64MachineFunctionInfo.h
ARM64MCInstLower.cpp
ARM64MCInstLower.h
ARM64PerfectShuffle.h
ARM64PromoteConstant.cpp
ARM64RegisterInfo.cpp
ARM64RegisterInfo.h
ARM64RegisterInfo.td
ARM64SchedA53.td	[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.	2014-05-19 22:59:51 +00:00
ARM64SchedCyclone.td
ARM64Schedule.td	[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.	2014-05-19 22:59:51 +00:00
ARM64SelectionDAGInfo.cpp	Target: remove old constructors for CallLoweringInfo	2014-05-17 21:50:17 +00:00
ARM64SelectionDAGInfo.h
ARM64StorePairSuppress.cpp
ARM64Subtarget.cpp
ARM64Subtarget.h
ARM64TargetMachine.cpp
ARM64TargetMachine.h
ARM64TargetObjectFile.cpp
ARM64TargetObjectFile.h
ARM64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile