llvm-6502/lib/Target/Sparc
Eric Christopher acdd4442cb getRegForInlineAsmConstraint wants to use TargetRegisterInfo for
a lookup, pass that in rather than use a naked call to getSubtargetImpl.
This involved passing down and around either a TargetMachine or
TargetRegisterInfo. Update all callers/definitions around the targets
and SelectionDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230699 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-26 22:38:43 +00:00
..
AsmParser Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers. 2015-01-03 08:16:34 +00:00
Disassembler
InstPrinter Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. 2015-02-19 11:38:11 +00:00
MCTargetDesc Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition. 2015-02-15 22:54:22 +00:00
TargetInfo
CMakeLists.txt
DelaySlotFiller.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
LLVMBuild.txt
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcCallingConv.td
SparcFrameLowering.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcFrameLowering.h
SparcInstr64Bit.td
SparcInstrAliases.td
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcInstrVIS.td
SparcISelDAGToDAG.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcISelLowering.cpp getRegForInlineAsmConstraint wants to use TargetRegisterInfo for 2015-02-26 22:38:43 +00:00
SparcISelLowering.h getRegForInlineAsmConstraint wants to use TargetRegisterInfo for 2015-02-26 22:38:43 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcSubtarget.h Move DataLayout back to the TargetMachine from TargetSubtargetInfo 2015-01-26 19:03:15 +00:00
SparcTargetMachine.cpp [PM] Remove the old 'PassManager.h' header file at the top level of 2015-02-13 10:01:29 +00:00
SparcTargetMachine.h Move DataLayout back to the TargetMachine from TargetSubtargetInfo 2015-01-26 19:03:15 +00:00
SparcTargetObjectFile.cpp
SparcTargetObjectFile.h
SparcTargetStreamer.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.