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https://github.com/c64scene-ar/llvm-6502.git
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36d29bc723
These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
750 B
LLVM
34 lines
750 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate new value jump.
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@i = global i32 0, align 4
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@j = global i32 10, align 4
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define i32 @foo(i32 %a) nounwind {
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entry:
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; CHECK: if (cmp.eq(r{{[0-9]+}}.new, #0)) jump{{.}}
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%addr1 = alloca i32, align 4
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%addr2 = alloca i32, align 4
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%0 = load i32* @i, align 4
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store i32 %0, i32* %addr1, align 4
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call void @bar(i32 1, i32 2)
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%1 = load i32* @j, align 4
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%tobool = icmp ne i32 %1, 0
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br i1 %tobool, label %if.then, label %if.else
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if.then:
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call void @baz(i32 1, i32 2)
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br label %if.end
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if.else:
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call void @guy(i32 10, i32 20)
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br label %if.end
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if.end:
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ret i32 0
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}
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declare void @guy(i32, i32)
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declare void @bar(i32, i32)
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declare void @baz(i32, i32)
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