mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
ca795b61be
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
727 lines
20 KiB
LLVM
727 lines
20 KiB
LLVM
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: add_v16i8:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = add <16 x i8> %1, %2
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; CHECK-DAG: addv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <16 x i8> %3, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size add_v16i8
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}
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define void @add_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
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; CHECK: add_v8i16:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = add <8 x i16> %1, %2
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; CHECK-DAG: addv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <8 x i16> %3, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size add_v8i16
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}
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define void @add_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
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; CHECK: add_v4i32:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = add <4 x i32> %1, %2
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; CHECK-DAG: addv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x i32> %3, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size add_v4i32
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}
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define void @add_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: add_v2i64:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = add <2 x i64> %1, %2
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; CHECK-DAG: addv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x i64> %3, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size add_v2i64
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}
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define void @add_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
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; CHECK: add_v16i8_i:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = add <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
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i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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; CHECK-DAG: addvi.b [[R3:\$w[0-9]+]], [[R1]], 1
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store <16 x i8> %2, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size add_v16i8_i
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}
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define void @add_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
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; CHECK: add_v8i16_i:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = add <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
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i16 1, i16 1, i16 1, i16 1>
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; CHECK-DAG: addvi.h [[R3:\$w[0-9]+]], [[R1]], 1
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store <8 x i16> %2, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size add_v8i16_i
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}
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define void @add_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
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; CHECK: add_v4i32_i:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = add <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
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; CHECK-DAG: addvi.w [[R3:\$w[0-9]+]], [[R1]], 1
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store <4 x i32> %2, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size add_v4i32_i
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}
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define void @add_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
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; CHECK: add_v2i64_i:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = add <2 x i64> %1, <i64 1, i64 1>
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; CHECK-DAG: addvi.d [[R3:\$w[0-9]+]], [[R1]], 1
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store <2 x i64> %2, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size add_v2i64_i
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}
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define void @sub_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: sub_v16i8:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = sub <16 x i8> %1, %2
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; CHECK-DAG: subv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <16 x i8> %3, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v16i8
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}
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define void @sub_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
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; CHECK: sub_v8i16:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = sub <8 x i16> %1, %2
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; CHECK-DAG: subv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <8 x i16> %3, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v8i16
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}
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define void @sub_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
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; CHECK: sub_v4i32:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = sub <4 x i32> %1, %2
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; CHECK-DAG: subv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x i32> %3, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v4i32
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}
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define void @sub_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: sub_v2i64:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = sub <2 x i64> %1, %2
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; CHECK-DAG: subv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x i64> %3, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v2i64
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}
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define void @sub_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
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; CHECK: sub_v16i8_i:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = sub <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
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i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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; CHECK-DAG: subvi.b [[R3:\$w[0-9]+]], [[R1]], 1
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store <16 x i8> %2, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v16i8_i
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}
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define void @sub_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
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; CHECK: sub_v8i16_i:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = sub <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1,
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i16 1, i16 1, i16 1, i16 1>
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; CHECK-DAG: subvi.h [[R3:\$w[0-9]+]], [[R1]], 1
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store <8 x i16> %2, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v8i16_i
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}
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define void @sub_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
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; CHECK: sub_v4i32_i:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = sub <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
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; CHECK-DAG: subvi.w [[R3:\$w[0-9]+]], [[R1]], 1
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store <4 x i32> %2, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v4i32_i
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}
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define void @sub_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
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; CHECK: sub_v2i64_i:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = sub <2 x i64> %1, <i64 1, i64 1>
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; CHECK-DAG: subvi.d [[R3:\$w[0-9]+]], [[R1]], 1
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store <2 x i64> %2, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v2i64_i
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}
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define void @mul_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: mul_v16i8:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = mul <16 x i8> %1, %2
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; CHECK-DAG: mulv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <16 x i8> %3, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v16i8
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}
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define void @mul_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
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; CHECK: mul_v8i16:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = mul <8 x i16> %1, %2
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; CHECK-DAG: mulv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <8 x i16> %3, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v8i16
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}
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define void @mul_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
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; CHECK: mul_v4i32:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = mul <4 x i32> %1, %2
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; CHECK-DAG: mulv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x i32> %3, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v4i32
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}
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define void @mul_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: mul_v2i64:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = mul <2 x i64> %1, %2
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; CHECK-DAG: mulv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x i64> %3, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v2i64
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}
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define void @maddv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
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<16 x i8>* %c) nounwind {
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; CHECK: maddv_v16i8:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = load <16 x i8>* %c
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; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <16 x i8> %2, %3
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%5 = add <16 x i8> %4, %1
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; CHECK-DAG: maddv.b [[R1]], [[R2]], [[R3]]
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store <16 x i8> %5, <16 x i8>* %d
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; CHECK-DAG: st.b [[R1]], 0($4)
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ret void
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; CHECK: .size maddv_v16i8
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}
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define void @maddv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
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<8 x i16>* %c) nounwind {
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; CHECK: maddv_v8i16:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = load <8 x i16>* %c
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; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
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%4 = mul <8 x i16> %2, %3
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%5 = add <8 x i16> %4, %1
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; CHECK-DAG: maddv.h [[R1]], [[R2]], [[R3]]
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store <8 x i16> %5, <8 x i16>* %d
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; CHECK-DAG: st.h [[R1]], 0($4)
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ret void
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; CHECK: .size maddv_v8i16
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}
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define void @maddv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
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<4 x i32>* %c) nounwind {
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; CHECK: maddv_v4i32:
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%1 = load <4 x i32>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <4 x i32>* %b
|
|
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = load <4 x i32>* %c
|
|
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
|
|
%4 = mul <4 x i32> %2, %3
|
|
%5 = add <4 x i32> %4, %1
|
|
; CHECK-DAG: maddv.w [[R1]], [[R2]], [[R3]]
|
|
store <4 x i32> %5, <4 x i32>* %d
|
|
; CHECK-DAG: st.w [[R1]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size maddv_v4i32
|
|
}
|
|
|
|
define void @maddv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
|
|
<2 x i64>* %c) nounwind {
|
|
; CHECK: maddv_v2i64:
|
|
|
|
%1 = load <2 x i64>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <2 x i64>* %b
|
|
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = load <2 x i64>* %c
|
|
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
|
|
%4 = mul <2 x i64> %2, %3
|
|
%5 = add <2 x i64> %4, %1
|
|
; CHECK-DAG: maddv.d [[R1]], [[R2]], [[R3]]
|
|
store <2 x i64> %5, <2 x i64>* %d
|
|
; CHECK-DAG: st.d [[R1]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size maddv_v2i64
|
|
}
|
|
|
|
define void @msubv_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
|
|
<16 x i8>* %c) nounwind {
|
|
; CHECK: msubv_v16i8:
|
|
|
|
%1 = load <16 x i8>* %a
|
|
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <16 x i8>* %b
|
|
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = load <16 x i8>* %c
|
|
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
|
|
%4 = mul <16 x i8> %2, %3
|
|
%5 = sub <16 x i8> %1, %4
|
|
; CHECK-DAG: msubv.b [[R1]], [[R2]], [[R3]]
|
|
store <16 x i8> %5, <16 x i8>* %d
|
|
; CHECK-DAG: st.b [[R1]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size msubv_v16i8
|
|
}
|
|
|
|
define void @msubv_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
|
|
<8 x i16>* %c) nounwind {
|
|
; CHECK: msubv_v8i16:
|
|
|
|
%1 = load <8 x i16>* %a
|
|
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <8 x i16>* %b
|
|
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = load <8 x i16>* %c
|
|
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
|
|
%4 = mul <8 x i16> %2, %3
|
|
%5 = sub <8 x i16> %1, %4
|
|
; CHECK-DAG: msubv.h [[R1]], [[R2]], [[R3]]
|
|
store <8 x i16> %5, <8 x i16>* %d
|
|
; CHECK-DAG: st.h [[R1]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size msubv_v8i16
|
|
}
|
|
|
|
define void @msubv_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
|
|
<4 x i32>* %c) nounwind {
|
|
; CHECK: msubv_v4i32:
|
|
|
|
%1 = load <4 x i32>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <4 x i32>* %b
|
|
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = load <4 x i32>* %c
|
|
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
|
|
%4 = mul <4 x i32> %2, %3
|
|
%5 = sub <4 x i32> %1, %4
|
|
; CHECK-DAG: msubv.w [[R1]], [[R2]], [[R3]]
|
|
store <4 x i32> %5, <4 x i32>* %d
|
|
; CHECK-DAG: st.w [[R1]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size msubv_v4i32
|
|
}
|
|
|
|
define void @msubv_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
|
|
<2 x i64>* %c) nounwind {
|
|
; CHECK: msubv_v2i64:
|
|
|
|
%1 = load <2 x i64>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <2 x i64>* %b
|
|
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = load <2 x i64>* %c
|
|
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
|
|
%4 = mul <2 x i64> %2, %3
|
|
%5 = sub <2 x i64> %1, %4
|
|
; CHECK-DAG: msubv.d [[R1]], [[R2]], [[R3]]
|
|
store <2 x i64> %5, <2 x i64>* %d
|
|
; CHECK-DAG: st.d [[R1]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size msubv_v2i64
|
|
}
|
|
|
|
define void @div_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
|
|
; CHECK: div_s_v16i8:
|
|
|
|
%1 = load <16 x i8>* %a
|
|
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <16 x i8>* %b
|
|
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = sdiv <16 x i8> %1, %2
|
|
; CHECK-DAG: div_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <16 x i8> %3, <16 x i8>* %c
|
|
; CHECK-DAG: st.b [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_s_v16i8
|
|
}
|
|
|
|
define void @div_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
|
|
; CHECK: div_s_v8i16:
|
|
|
|
%1 = load <8 x i16>* %a
|
|
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <8 x i16>* %b
|
|
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = sdiv <8 x i16> %1, %2
|
|
; CHECK-DAG: div_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <8 x i16> %3, <8 x i16>* %c
|
|
; CHECK-DAG: st.h [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_s_v8i16
|
|
}
|
|
|
|
define void @div_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
|
|
; CHECK: div_s_v4i32:
|
|
|
|
%1 = load <4 x i32>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <4 x i32>* %b
|
|
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = sdiv <4 x i32> %1, %2
|
|
; CHECK-DAG: div_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <4 x i32> %3, <4 x i32>* %c
|
|
; CHECK-DAG: st.w [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_s_v4i32
|
|
}
|
|
|
|
define void @div_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
|
|
; CHECK: div_s_v2i64:
|
|
|
|
%1 = load <2 x i64>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <2 x i64>* %b
|
|
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = sdiv <2 x i64> %1, %2
|
|
; CHECK-DAG: div_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <2 x i64> %3, <2 x i64>* %c
|
|
; CHECK-DAG: st.d [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_s_v2i64
|
|
}
|
|
|
|
define void @div_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
|
|
; CHECK: div_u_v16i8:
|
|
|
|
%1 = load <16 x i8>* %a
|
|
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <16 x i8>* %b
|
|
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = udiv <16 x i8> %1, %2
|
|
; CHECK-DAG: div_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <16 x i8> %3, <16 x i8>* %c
|
|
; CHECK-DAG: st.b [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_u_v16i8
|
|
}
|
|
|
|
define void @div_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
|
|
; CHECK: div_u_v8i16:
|
|
|
|
%1 = load <8 x i16>* %a
|
|
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <8 x i16>* %b
|
|
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = udiv <8 x i16> %1, %2
|
|
; CHECK-DAG: div_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <8 x i16> %3, <8 x i16>* %c
|
|
; CHECK-DAG: st.h [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_u_v8i16
|
|
}
|
|
|
|
define void @div_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
|
|
; CHECK: div_u_v4i32:
|
|
|
|
%1 = load <4 x i32>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <4 x i32>* %b
|
|
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = udiv <4 x i32> %1, %2
|
|
; CHECK-DAG: div_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <4 x i32> %3, <4 x i32>* %c
|
|
; CHECK-DAG: st.w [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_u_v4i32
|
|
}
|
|
|
|
define void @div_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
|
|
; CHECK: div_u_v2i64:
|
|
|
|
%1 = load <2 x i64>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <2 x i64>* %b
|
|
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = udiv <2 x i64> %1, %2
|
|
; CHECK-DAG: div_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <2 x i64> %3, <2 x i64>* %c
|
|
; CHECK-DAG: st.d [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size div_u_v2i64
|
|
}
|
|
|
|
define void @mod_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
|
|
; CHECK: mod_s_v16i8:
|
|
|
|
%1 = load <16 x i8>* %a
|
|
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <16 x i8>* %b
|
|
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = srem <16 x i8> %1, %2
|
|
; CHECK-DAG: mod_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <16 x i8> %3, <16 x i8>* %c
|
|
; CHECK-DAG: st.b [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_s_v16i8
|
|
}
|
|
|
|
define void @mod_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
|
|
; CHECK: mod_s_v8i16:
|
|
|
|
%1 = load <8 x i16>* %a
|
|
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <8 x i16>* %b
|
|
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = srem <8 x i16> %1, %2
|
|
; CHECK-DAG: mod_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <8 x i16> %3, <8 x i16>* %c
|
|
; CHECK-DAG: st.h [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_s_v8i16
|
|
}
|
|
|
|
define void @mod_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
|
|
; CHECK: mod_s_v4i32:
|
|
|
|
%1 = load <4 x i32>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <4 x i32>* %b
|
|
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = srem <4 x i32> %1, %2
|
|
; CHECK-DAG: mod_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <4 x i32> %3, <4 x i32>* %c
|
|
; CHECK-DAG: st.w [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_s_v4i32
|
|
}
|
|
|
|
define void @mod_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
|
|
; CHECK: mod_s_v2i64:
|
|
|
|
%1 = load <2 x i64>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <2 x i64>* %b
|
|
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = srem <2 x i64> %1, %2
|
|
; CHECK-DAG: mod_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <2 x i64> %3, <2 x i64>* %c
|
|
; CHECK-DAG: st.d [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_s_v2i64
|
|
}
|
|
|
|
define void @mod_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
|
|
; CHECK: mod_u_v16i8:
|
|
|
|
%1 = load <16 x i8>* %a
|
|
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <16 x i8>* %b
|
|
; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = urem <16 x i8> %1, %2
|
|
; CHECK-DAG: mod_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <16 x i8> %3, <16 x i8>* %c
|
|
; CHECK-DAG: st.b [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_u_v16i8
|
|
}
|
|
|
|
define void @mod_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
|
|
; CHECK: mod_u_v8i16:
|
|
|
|
%1 = load <8 x i16>* %a
|
|
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <8 x i16>* %b
|
|
; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = urem <8 x i16> %1, %2
|
|
; CHECK-DAG: mod_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <8 x i16> %3, <8 x i16>* %c
|
|
; CHECK-DAG: st.h [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_u_v8i16
|
|
}
|
|
|
|
define void @mod_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
|
|
; CHECK: mod_u_v4i32:
|
|
|
|
%1 = load <4 x i32>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <4 x i32>* %b
|
|
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = urem <4 x i32> %1, %2
|
|
; CHECK-DAG: mod_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <4 x i32> %3, <4 x i32>* %c
|
|
; CHECK-DAG: st.w [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_u_v4i32
|
|
}
|
|
|
|
define void @mod_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
|
|
; CHECK: mod_u_v2i64:
|
|
|
|
%1 = load <2 x i64>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = load <2 x i64>* %b
|
|
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
|
|
%3 = urem <2 x i64> %1, %2
|
|
; CHECK-DAG: mod_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
|
store <2 x i64> %3, <2 x i64>* %c
|
|
; CHECK-DAG: st.d [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size mod_u_v2i64
|
|
}
|