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https://github.com/c64scene-ar/llvm-6502.git
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23ed37a6b7
This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
617 lines
22 KiB
C++
617 lines
22 KiB
C++
//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCREGISTERINFO_H
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#define LLVM_MC_MCREGISTERINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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namespace llvm {
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/// An unsigned integer type large enough to represent all physical registers,
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/// but not necessarily virtual registers.
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typedef uint16_t MCPhysReg;
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/// MCRegisterClass - Base class of TargetRegisterClass.
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class MCRegisterClass {
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public:
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typedef const MCPhysReg* iterator;
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typedef const MCPhysReg* const_iterator;
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const char *Name;
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const iterator RegsBegin;
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const uint8_t *const RegSet;
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const uint16_t RegsSize;
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const uint16_t RegSetSize;
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const uint16_t ID;
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const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
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const int8_t CopyCost;
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const bool Allocatable;
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/// getID() - Return the register class ID number.
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///
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unsigned getID() const { return ID; }
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/// getName() - Return the register class name for debugging.
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///
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const char *getName() const { return Name; }
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/// begin/end - Return all of the registers in this class.
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///
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iterator begin() const { return RegsBegin; }
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iterator end() const { return RegsBegin + RegsSize; }
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/// getNumRegs - Return the number of registers in this class.
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///
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unsigned getNumRegs() const { return RegsSize; }
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/// getRegister - Return the specified register in the class.
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///
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unsigned getRegister(unsigned i) const {
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assert(i < getNumRegs() && "Register number out of range!");
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return RegsBegin[i];
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}
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/// contains - Return true if the specified register is included in this
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/// register class. This does not include virtual registers.
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bool contains(unsigned Reg) const {
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unsigned InByte = Reg % 8;
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unsigned Byte = Reg / 8;
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if (Byte >= RegSetSize)
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return false;
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return (RegSet[Byte] & (1 << InByte)) != 0;
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}
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/// contains - Return true if both registers are in this class.
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bool contains(unsigned Reg1, unsigned Reg2) const {
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return contains(Reg1) && contains(Reg2);
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return RegSize; }
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/// getAlignment - Return the minimum required alignment for a register of
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/// this class.
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unsigned getAlignment() const { return Alignment; }
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/// getCopyCost - Return the cost of copying a value between two registers in
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/// this class. A negative number means the register class is very expensive
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/// to copy e.g. status flag register classes.
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int getCopyCost() const { return CopyCost; }
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/// isAllocatable - Return true if this register class may be used to create
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/// virtual registers.
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bool isAllocatable() const { return Allocatable; }
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};
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/// MCRegisterDesc - This record contains information about a particular
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/// register. The SubRegs field is a zero terminated array of registers that
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/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
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/// of AX. The SuperRegs field is a zero terminated array of registers that are
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/// super-registers of the specific register, e.g. RAX, EAX, are
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/// super-registers of AX.
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///
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struct MCRegisterDesc {
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uint32_t Name; // Printable name for the reg (for debugging)
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uint32_t SubRegs; // Sub-register set, described above
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uint32_t SuperRegs; // Super-register set, described above
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// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
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// sub-register in SubRegs.
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uint32_t SubRegIndices;
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// RegUnits - Points to the list of register units. The low 4 bits holds the
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// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
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uint32_t RegUnits;
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};
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/// MCRegisterInfo base class - We assume that the target defines a static
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/// array of MCRegisterDesc objects that represent all of the machine
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/// registers that the target has. As such, we simply have to track a pointer
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/// to this array so that we can turn register number into a register
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/// descriptor.
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///
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/// Note this class is designed to be a base class of TargetRegisterInfo, which
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/// is the interface used by codegen. However, specific targets *should never*
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/// specialize this class. MCRegisterInfo should only contain getters to access
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/// TableGen generated physical register data. It must not be extended with
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/// virtual methods.
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///
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class MCRegisterInfo {
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public:
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typedef const MCRegisterClass *regclass_iterator;
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/// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
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/// performed with a binary search.
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struct DwarfLLVMRegPair {
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unsigned FromReg;
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unsigned ToReg;
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bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
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};
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/// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
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/// index, -1 in any being invalid.
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struct SubRegCoveredBits {
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uint16_t Offset;
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uint16_t Size;
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};
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private:
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const MCRegisterDesc *Desc; // Pointer to the descriptor array
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unsigned NumRegs; // Number of entries in the array
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unsigned RAReg; // Return address register
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unsigned PCReg; // Program counter register
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const MCRegisterClass *Classes; // Pointer to the regclass array
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unsigned NumClasses; // Number of entries in the array
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unsigned NumRegUnits; // Number of regunits.
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const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
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const MCPhysReg *DiffLists; // Pointer to the difflists array
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const char *RegStrings; // Pointer to the string table.
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const uint16_t *SubRegIndices; // Pointer to the subreg lookup
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// array.
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const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
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// bit ranges array.
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unsigned NumSubRegIndices; // Number of subreg indices.
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const uint16_t *RegEncodingTable; // Pointer to array of register
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// encodings.
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unsigned L2DwarfRegsSize;
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unsigned EHL2DwarfRegsSize;
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unsigned Dwarf2LRegsSize;
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unsigned EHDwarf2LRegsSize;
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const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
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const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
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const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
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const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
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DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
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public:
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/// DiffListIterator - Base iterator class that can traverse the
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/// differentially encoded register and regunit lists in DiffLists.
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/// Don't use this class directly, use one of the specialized sub-classes
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/// defined below.
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class DiffListIterator {
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uint16_t Val;
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const MCPhysReg *List;
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protected:
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/// Create an invalid iterator. Call init() to point to something useful.
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DiffListIterator() : Val(0), List(0) {}
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/// init - Point the iterator to InitVal, decoding subsequent values from
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/// DiffList. The iterator will initially point to InitVal, sub-classes are
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/// responsible for skipping the seed value if it is not part of the list.
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void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
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Val = InitVal;
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List = DiffList;
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}
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/// advance - Move to the next list position, return the applied
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/// differential. This function does not detect the end of the list, that
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/// is the caller's responsibility (by checking for a 0 return value).
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unsigned advance() {
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assert(isValid() && "Cannot move off the end of the list.");
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MCPhysReg D = *List++;
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Val += D;
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return D;
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}
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public:
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/// isValid - returns true if this iterator is not yet at the end.
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bool isValid() const { return List; }
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/// Dereference the iterator to get the value at the current position.
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unsigned operator*() const { return Val; }
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/// Pre-increment to move to the next position.
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void operator++() {
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// The end of the list is encoded as a 0 differential.
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if (!advance())
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List = 0;
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}
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};
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// These iterators are allowed to sub-class DiffListIterator and access
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// internal list pointers.
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friend class MCSubRegIterator;
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friend class MCSuperRegIterator;
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friend class MCRegUnitIterator;
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friend class MCRegUnitRootIterator;
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/// \brief Initialize MCRegisterInfo, called by TableGen
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/// auto-generated routines. *DO NOT USE*.
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void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
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unsigned PC,
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const MCRegisterClass *C, unsigned NC,
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const uint16_t (*RURoots)[2],
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unsigned NRU,
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const MCPhysReg *DL,
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const char *Strings,
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const uint16_t *SubIndices,
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unsigned NumIndices,
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const SubRegCoveredBits *SubIdxRanges,
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const uint16_t *RET) {
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Desc = D;
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NumRegs = NR;
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RAReg = RA;
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PCReg = PC;
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Classes = C;
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DiffLists = DL;
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RegStrings = Strings;
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NumClasses = NC;
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RegUnitRoots = RURoots;
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NumRegUnits = NRU;
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SubRegIndices = SubIndices;
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NumSubRegIndices = NumIndices;
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SubRegIdxRanges = SubIdxRanges;
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RegEncodingTable = RET;
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}
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/// \brief Used to initialize LLVM register to Dwarf
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/// register number mapping. Called by TableGen auto-generated routines.
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/// *DO NOT USE*.
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void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
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bool isEH) {
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if (isEH) {
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EHL2DwarfRegs = Map;
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EHL2DwarfRegsSize = Size;
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} else {
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L2DwarfRegs = Map;
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L2DwarfRegsSize = Size;
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}
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}
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/// \brief Used to initialize Dwarf register to LLVM
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/// register number mapping. Called by TableGen auto-generated routines.
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/// *DO NOT USE*.
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void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
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bool isEH) {
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if (isEH) {
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EHDwarf2LRegs = Map;
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EHDwarf2LRegsSize = Size;
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} else {
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Dwarf2LRegs = Map;
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Dwarf2LRegsSize = Size;
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}
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}
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/// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
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/// number mapping. By default the SEH register number is just the same
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/// as the LLVM register number.
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/// FIXME: TableGen these numbers. Currently this requires target specific
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/// initialization code.
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void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
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L2SEHRegs[LLVMReg] = SEHReg;
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}
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/// \brief This method should return the register where the return
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/// address can be found.
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unsigned getRARegister() const {
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return RAReg;
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}
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/// Return the register which is the program counter.
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unsigned getProgramCounter() const {
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return PCReg;
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}
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const MCRegisterDesc &operator[](unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to access record for invalid register number!");
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return Desc[RegNo];
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}
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/// \brief Provide a get method, equivalent to [], but more useful with a
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/// pointer to this object.
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const MCRegisterDesc &get(unsigned RegNo) const {
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return operator[](RegNo);
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}
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/// \brief Returns the physical register number of sub-register "Index"
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/// for physical register RegNo. Return zero if the sub-register does not
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/// exist.
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unsigned getSubReg(unsigned Reg, unsigned Idx) const;
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/// \brief Return a super-register of the specified register
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/// Reg so its sub-register of index SubIdx is Reg.
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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const MCRegisterClass *RC) const;
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/// \brief For a given register pair, return the sub-register index
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/// if the second register is a sub-register of the first. Return zero
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/// otherwise.
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unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
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/// \brief Get the size of the bit range covered by a sub-register index.
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/// If the index isn't continuous, return the sum of the sizes of its parts.
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/// If the index is used to access subregisters of different sizes, return -1.
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unsigned getSubRegIdxSize(unsigned Idx) const;
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/// \brief Get the offset of the bit range covered by a sub-register index.
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/// If an Offset doesn't make sense (the index isn't continuous, or is used to
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/// access sub-registers at different offsets), return -1.
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unsigned getSubRegIdxOffset(unsigned Idx) const;
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/// \brief Return the human-readable symbolic target-specific name for the
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/// specified physical register.
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const char *getName(unsigned RegNo) const {
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return RegStrings + get(RegNo).Name;
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}
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/// \brief Return the number of registers this target has (useful for
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/// sizing arrays holding per register information)
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unsigned getNumRegs() const {
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return NumRegs;
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}
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/// \brief Return the number of sub-register indices
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/// understood by the target. Index 0 is reserved for the no-op sub-register,
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/// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
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unsigned getNumSubRegIndices() const {
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return NumSubRegIndices;
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}
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/// \brief Return the number of (native) register units in the
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/// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
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/// can be accessed through MCRegUnitIterator defined below.
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unsigned getNumRegUnits() const {
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return NumRegUnits;
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}
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/// \brief Map a target register to an equivalent dwarf register
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/// number. Returns -1 if there is no equivalent value. The second
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/// parameter allows targets to use different numberings for EH info and
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/// debugging info.
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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/// \brief Map a dwarf register back to a target register.
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int getLLVMRegNum(unsigned RegNum, bool isEH) const;
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/// \brief Map a target register to an equivalent SEH register
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/// number. Returns LLVM register number if there is no equivalent value.
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int getSEHRegNum(unsigned RegNum) const;
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regclass_iterator regclass_begin() const { return Classes; }
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regclass_iterator regclass_end() const { return Classes+NumClasses; }
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unsigned getNumRegClasses() const {
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return (unsigned)(regclass_end()-regclass_begin());
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}
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/// \brief Returns the register class associated with the enumeration
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/// value. See class MCOperandInfo.
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const MCRegisterClass& getRegClass(unsigned i) const {
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assert(i < getNumRegClasses() && "Register Class ID out of range");
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return Classes[i];
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}
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/// \brief Returns the encoding for RegNo
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uint16_t getEncodingValue(unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to get encoding for invalid register number!");
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return RegEncodingTable[RegNo];
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}
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/// \brief Returns true if RegB is a sub-register of RegA.
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bool isSubRegister(unsigned RegA, unsigned RegB) const {
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return isSuperRegister(RegB, RegA);
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}
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/// \brief Returns true if RegB is a super-register of RegA.
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bool isSuperRegister(unsigned RegA, unsigned RegB) const;
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/// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
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bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
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return isSuperRegisterEq(RegB, RegA);
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}
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/// \brief Returns true if RegB is a super-register of RegA or if
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/// RegB == RegA.
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bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
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return RegA == RegB || isSuperRegister(RegA, RegB);
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}
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};
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//===----------------------------------------------------------------------===//
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// Register List Iterators
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//===----------------------------------------------------------------------===//
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// MCRegisterInfo provides lists of super-registers, sub-registers, and
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// aliasing registers. Use these iterator classes to traverse the lists.
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/// MCSubRegIterator enumerates all sub-registers of Reg.
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/// If IncludeSelf is set, Reg itself is included in the list.
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class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
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public:
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MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
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bool IncludeSelf = false) {
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init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
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// Initially, the iterator points to Reg itself.
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if (!IncludeSelf)
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++*this;
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}
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};
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/// MCSuperRegIterator enumerates all super-registers of Reg.
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/// If IncludeSelf is set, Reg itself is included in the list.
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class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
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public:
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MCSuperRegIterator() {}
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MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
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bool IncludeSelf = false) {
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init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
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// Initially, the iterator points to Reg itself.
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if (!IncludeSelf)
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++*this;
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}
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};
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// Definition for isSuperRegister. Put it down here since it needs the
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// iterator defined above in addition to the MCRegisterInfo class itself.
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inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
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for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
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if (*I == RegB)
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return true;
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return false;
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}
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//===----------------------------------------------------------------------===//
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// Register Units
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//===----------------------------------------------------------------------===//
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// Register units are used to compute register aliasing. Every register has at
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// least one register unit, but it can have more. Two registers overlap if and
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// only if they have a common register unit.
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//
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// A target with a complicated sub-register structure will typically have many
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// fewer register units than actual registers. MCRI::getNumRegUnits() returns
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// the number of register units in the target.
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// MCRegUnitIterator enumerates a list of register units for Reg. The list is
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// in ascending numerical order.
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class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
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public:
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/// MCRegUnitIterator - Create an iterator that traverses the register units
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/// in Reg.
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MCRegUnitIterator() {}
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MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
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assert(Reg && "Null register has no regunits");
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// Decode the RegUnits MCRegisterDesc field.
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unsigned RU = MCRI->get(Reg).RegUnits;
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unsigned Scale = RU & 15;
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unsigned Offset = RU >> 4;
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// Initialize the iterator to Reg * Scale, and the List pointer to
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// DiffLists + Offset.
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init(Reg * Scale, MCRI->DiffLists + Offset);
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// That may not be a valid unit, we need to advance by one to get the real
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// unit number. The first differential can be 0 which would normally
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// terminate the list, but since we know every register has at least one
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// unit, we can allow a 0 differential here.
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advance();
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}
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};
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// Each register unit has one or two root registers. The complete set of
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// registers containing a register unit is the union of the roots and their
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// super-registers. All registers aliasing Unit can be visited like this:
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//
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// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
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// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
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// visit(*SI);
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// }
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/// MCRegUnitRootIterator enumerates the root registers of a register unit.
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class MCRegUnitRootIterator {
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uint16_t Reg0;
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uint16_t Reg1;
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public:
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MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
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MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
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assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
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Reg0 = MCRI->RegUnitRoots[RegUnit][0];
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Reg1 = MCRI->RegUnitRoots[RegUnit][1];
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}
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/// \brief Dereference to get the current root register.
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unsigned operator*() const {
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return Reg0;
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}
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/// \brief Check if the iterator is at the end of the list.
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bool isValid() const {
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return Reg0;
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}
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/// \brief Preincrement to move to the next root register.
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void operator++() {
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assert(isValid() && "Cannot move off the end of the list.");
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Reg0 = Reg1;
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Reg1 = 0;
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}
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};
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/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
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/// set, Reg itself is included in the list. This iterator does not guarantee
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/// any ordering or that entries are unique.
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class MCRegAliasIterator {
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private:
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unsigned Reg;
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const MCRegisterInfo *MCRI;
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bool IncludeSelf;
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MCRegUnitIterator RI;
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MCRegUnitRootIterator RRI;
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MCSuperRegIterator SI;
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public:
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MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
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bool IncludeSelf)
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: Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
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// Initialize the iterators.
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for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
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for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
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for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
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if (!(!IncludeSelf && Reg == *SI))
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return;
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}
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}
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}
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}
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bool isValid() const {
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return RI.isValid();
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}
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|
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unsigned operator*() const {
|
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assert (SI.isValid() && "Cannot dereference an invalid iterator.");
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return *SI;
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}
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|
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void advance() {
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// Assuming SI is valid.
|
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++SI;
|
|
if (SI.isValid()) return;
|
|
|
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++RRI;
|
|
if (RRI.isValid()) {
|
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SI = MCSuperRegIterator(*RRI, MCRI, true);
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return;
|
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}
|
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|
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++RI;
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if (RI.isValid()) {
|
|
RRI = MCRegUnitRootIterator(*RI, MCRI);
|
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SI = MCSuperRegIterator(*RRI, MCRI, true);
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|
}
|
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}
|
|
|
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void operator++() {
|
|
assert(isValid() && "Cannot move off the end of the list.");
|
|
do advance();
|
|
while (!IncludeSelf && isValid() && *SI == Reg);
|
|
}
|
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};
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} // End llvm namespace
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#endif
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