mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-10 17:29:44 +00:00
055d207426
Incremental improvement to fast-isel for PPC64. This allows us to select on ret, sext, and zext. Filling in sext/zext improves some of the existing logic in handling compare-immediates that needed extends. A simplified return convention for fast-isel is also added to the PPC64 calling conventions. All call/return processing for DAG selection is handled with custom code, so there isn't an existing CC to rely on here. The include of PPCGenCallingConv.inc causes compiler warnings due to the 32-bit calling conventions that are not used, so the dummy function "usePPC32CCs()" is added here to silence those. Test cases for the return and extend logic are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189266 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
2.3 KiB
LLVM
143 lines
2.3 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret2
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; ELF64: extsb
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; ELF64: blr
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ret i8 %a
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}
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define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret3
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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; ELF64: blr
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ret i8 %a
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}
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define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret4
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; ELF64: extsh
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; ELF64: blr
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ret i16 %a
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}
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define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret5
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: blr
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ret i16 %a
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}
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define i16 @ret6(i16 %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret6
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: blr
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ret i16 %a
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}
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define signext i32 @ret7(i32 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret7
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; ELF64: extsw
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; ELF64: blr
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ret i32 %a
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}
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define zeroext i32 @ret8(i32 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret8
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
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; ELF64: blr
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ret i32 %a
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}
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define i32 @ret9(i32 %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret9
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
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; ELF64: blr
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ret i32 %a
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}
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define i64 @ret10(i64 %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret10
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; ELF64-NOT: exts
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; ELF64-NOT: rldicl
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; ELF64: blr
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ret i64 %a
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}
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define float @ret11(float %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret11
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; ELF64: blr
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ret float %a
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}
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define double @ret12(double %a) nounwind uwtable ssp {
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entry:
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; ELF64: ret12
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; ELF64: blr
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ret double %a
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}
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define i8 @ret13() nounwind uwtable ssp {
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entry:
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; ELF64: ret13
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; ELF64: li
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; ELF64: blr
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ret i8 15;
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}
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define i16 @ret14() nounwind uwtable ssp {
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entry:
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; ELF64: ret14
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; ELF64: li
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; ELF64: blr
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ret i16 -225;
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}
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define i32 @ret15() nounwind uwtable ssp {
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entry:
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; ELF64: ret15
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; ELF64: lis
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; ELF64: ori
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; ELF64: blr
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ret i32 278135;
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}
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define i64 @ret16() nounwind uwtable ssp {
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entry:
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; ELF64: ret16
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; ELF64: li
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; ELF64: sldi
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; ELF64: oris
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; ELF64: ori
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; ELF64: blr
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ret i64 27813515225;
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}
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define float @ret17() nounwind uwtable ssp {
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entry:
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; ELF64: ret17
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; ELF64: addis
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; ELF64: lfs
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; ELF64: blr
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ret float 2.5;
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}
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define double @ret18() nounwind uwtable ssp {
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entry:
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; ELF64: ret18
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; ELF64: addis
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; ELF64: lfd
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; ELF64: blr
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ret double 2.5e-33;
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}
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