mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e488e9360b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9312 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.9 KiB
Makefile
45 lines
1.9 KiB
Makefile
##===- lib/Target/X86/Makefile ----------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file was developed by the LLVM research group and is distributed under
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# the University of Illinois Open Source License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = x86
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include $(LEVEL)/Makefile.common
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenInstrSelector.inc
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X86GenRegisterNames.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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@echo "Building $< register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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@echo "Building $< register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
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@echo "Building $< register information implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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@echo "Building $< instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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@echo "Building $< instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
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@echo "Building $< instruction selector with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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clean::
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$(VERB) rm -f *.inc
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