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https://github.com/c64scene-ar/llvm-6502.git
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e573fb3255
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.
The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
vmov.i32 d1, #0x80000000
vbsl d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.2 KiB
LLVM
45 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT
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; RUN: llc < %s -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD
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; rdar://8984306
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define float @test1(float %x, float %y) nounwind {
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entry:
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; SOFT: test1:
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; SOFT: lsr r1, r1, #31
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; SOFT: bfi r0, r1, #31, #1
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; HARD: test1:
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; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000
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; HARD: vbsl [[REG1]], d2, d0
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%0 = tail call float @copysignf(float %x, float %y) nounwind
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ret float %0
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}
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define double @test2(double %x, double %y) nounwind {
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entry:
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; SOFT: test2:
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; SOFT: lsr r2, r3, #31
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; SOFT: bfi r1, r2, #31, #1
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; HARD: test2:
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; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
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; HARD: vshl.i64 [[REG2]], [[REG2]], #32
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; HARD: vbsl [[REG2]], d1, d0
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%0 = tail call double @copysign(double %x, double %y) nounwind
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ret double %0
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}
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define double @test3(double %x, double %y, double %z) nounwind {
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entry:
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; SOFT: test3:
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; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
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; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
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; SOFT: vbsl [[REG3]],
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%0 = fmul double %x, %y
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%1 = tail call double @copysign(double %0, double %z) nounwind
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ret double %1
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}
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declare double @copysign(double, double) nounwind
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declare float @copysignf(float, float) nounwind
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