mirror of
https://github.com/c64scene-ar/llvm-6502.git
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60e32b0776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30556 91177308-0d34-0410-b5e6-96231b3b80d8
754 lines
21 KiB
Plaintext
754 lines
21 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the X86 backend.
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//===---------------------------------------------------------------------===//
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Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
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Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
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X86, & make the dag combiner produce it when needed. This will eliminate one
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imul from the code generated for:
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long long test(long long X, long long Y) { return X*Y; }
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by using the EAX result from the mul. We should add a similar node for
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DIVREM.
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another case is:
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long long test(int X, int Y) { return (long long)X*Y; }
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... which should only be one imul instruction.
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This can be done with a custom expander, but it would be nice to move this to
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generic code.
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//===---------------------------------------------------------------------===//
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This should be one DIV/IDIV instruction, not a libcall:
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unsigned test(unsigned long long X, unsigned Y) {
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return X/Y;
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}
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This can be done trivially with a custom legalizer. What about overflow
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though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
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//===---------------------------------------------------------------------===//
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Improvements to the multiply -> shift/add algorithm:
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http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
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//===---------------------------------------------------------------------===//
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Improve code like this (occurs fairly frequently, e.g. in LLVM):
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long long foo(int x) { return 1LL << x; }
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
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http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
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Another useful one would be ~0ULL >> X and ~0ULL << X.
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One better solution for 1LL << x is:
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xorl %eax, %eax
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xorl %edx, %edx
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testb $32, %cl
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sete %al
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setne %dl
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sall %cl, %eax
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sall %cl, %edx
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But that requires good 8-bit subreg support.
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64-bit shifts (in general) expand to really bad code. Instead of using
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cmovs, we should expand to a conditional branch like GCC produces.
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//===---------------------------------------------------------------------===//
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Compile this:
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_Bool f(_Bool a) { return a!=1; }
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into:
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movzbl %dil, %eax
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xorl $1, %eax
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ret
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//===---------------------------------------------------------------------===//
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Some isel ideas:
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1. Dynamic programming based approach when compile time if not an
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issue.
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2. Code duplication (addressing mode) during isel.
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3. Other ideas from "Register-Sensitive Selection, Duplication, and
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Sequencing of Instructions".
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4. Scheduling for reduced register pressure. E.g. "Minimum Register
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Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
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and other related papers.
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http://citeseer.ist.psu.edu/govindarajan01minimum.html
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//===---------------------------------------------------------------------===//
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Should we promote i16 to i32 to avoid partial register update stalls?
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//===---------------------------------------------------------------------===//
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Leave any_extend as pseudo instruction and hint to register
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allocator. Delay codegen until post register allocation.
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//===---------------------------------------------------------------------===//
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Count leading zeros and count trailing zeros:
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int clz(int X) { return __builtin_clz(X); }
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int ctz(int X) { return __builtin_ctz(X); }
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$ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
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clz:
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bsr %eax, DWORD PTR [%esp+4]
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xor %eax, 31
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ret
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ctz:
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bsf %eax, DWORD PTR [%esp+4]
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ret
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however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
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aren't.
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//===---------------------------------------------------------------------===//
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Use push/pop instructions in prolog/epilog sequences instead of stores off
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ESP (certain code size win, perf win on some [which?] processors).
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Also, it appears icc use push for parameter passing. Need to investigate.
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//===---------------------------------------------------------------------===//
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Only use inc/neg/not instructions on processors where they are faster than
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add/sub/xor. They are slower on the P4 due to only updating some processor
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flags.
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//===---------------------------------------------------------------------===//
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The instruction selector sometimes misses folding a load into a compare. The
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pattern is written as (cmp reg, (load p)). Because the compare isn't
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commutative, it is not matched with the load on both sides. The dag combiner
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should be made smart enough to cannonicalize the load into the RHS of a compare
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when it can invert the result of the compare for free.
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//===---------------------------------------------------------------------===//
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How about intrinsics? An example is:
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*res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
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compiles to
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pmuludq (%eax), %xmm0
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movl 8(%esp), %eax
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movdqa (%eax), %xmm1
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pmulhuw %xmm0, %xmm1
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The transformation probably requires a X86 specific pass or a DAG combiner
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target specific hook.
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//===---------------------------------------------------------------------===//
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In many cases, LLVM generates code like this:
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_test:
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movl 8(%esp), %eax
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cmpl %eax, 4(%esp)
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setl %al
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movzbl %al, %eax
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ret
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on some processors (which ones?), it is more efficient to do this:
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_test:
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movl 8(%esp), %ebx
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xor %eax, %eax
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cmpl %ebx, 4(%esp)
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setl %al
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ret
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Doing this correctly is tricky though, as the xor clobbers the flags.
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//===---------------------------------------------------------------------===//
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We should generate bts/btr/etc instructions on targets where they are cheap or
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when codesize is important. e.g., for:
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void setbit(int *target, int bit) {
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*target |= (1 << bit);
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}
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void clearbit(int *target, int bit) {
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*target &= ~(1 << bit);
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}
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//===---------------------------------------------------------------------===//
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Instead of the following for memset char*, 1, 10:
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movl $16843009, 4(%edx)
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movl $16843009, (%edx)
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movw $257, 8(%edx)
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It might be better to generate
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movl $16843009, %eax
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movl %eax, 4(%edx)
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movl %eax, (%edx)
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movw al, 8(%edx)
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when we can spare a register. It reduces code size.
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//===---------------------------------------------------------------------===//
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Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
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get this:
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int %test1(int %X) {
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%Y = div int %X, 8
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ret int %Y
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}
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_test1:
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movl 4(%esp), %eax
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movl %eax, %ecx
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sarl $31, %ecx
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shrl $29, %ecx
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addl %ecx, %eax
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sarl $3, %eax
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ret
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GCC knows several different ways to codegen it, one of which is this:
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_test1:
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movl 4(%esp), %eax
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cmpl $-1, %eax
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leal 7(%eax), %ecx
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cmovle %ecx, %eax
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sarl $3, %eax
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ret
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which is probably slower, but it's interesting at least :)
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//===---------------------------------------------------------------------===//
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Should generate min/max for stuff like:
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void minf(float a, float b, float *X) {
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*X = a <= b ? a : b;
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}
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Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
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and ISD::FMAX node types?
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//===---------------------------------------------------------------------===//
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The first BB of this code:
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declare bool %foo()
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int %bar() {
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%V = call bool %foo()
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br bool %V, label %T, label %F
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T:
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ret int 1
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F:
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call bool %foo()
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ret int 12
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}
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compiles to:
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_bar:
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subl $12, %esp
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call L_foo$stub
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xorb $1, %al
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testb %al, %al
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jne LBB_bar_2 # F
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It would be better to emit "cmp %al, 1" than a xor and test.
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//===---------------------------------------------------------------------===//
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Enable X86InstrInfo::convertToThreeAddress().
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//===---------------------------------------------------------------------===//
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We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
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We should leave these as libcalls for everything over a much lower threshold,
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since libc is hand tuned for medium and large mem ops (avoiding RFO for large
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stores, TLB preheating, etc)
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//===---------------------------------------------------------------------===//
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Optimize this into something reasonable:
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x * copysign(1.0, y) * copysign(1.0, z)
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//===---------------------------------------------------------------------===//
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Optimize copysign(x, *y) to use an integer load from y.
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//===---------------------------------------------------------------------===//
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%X = weak global int 0
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void %foo(int %N) {
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%N = cast int %N to uint
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%tmp.24 = setgt int %N, 0
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br bool %tmp.24, label %no_exit, label %return
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no_exit:
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%indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
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%i.0.0 = cast uint %indvar to int
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volatile store int %i.0.0, int* %X
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%indvar.next = add uint %indvar, 1
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%exitcond = seteq uint %indvar.next, %N
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br bool %exitcond, label %return, label %no_exit
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return:
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ret void
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}
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compiles into:
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.text
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.align 4
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.globl _foo
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_foo:
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movl 4(%esp), %eax
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cmpl $1, %eax
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jl LBB_foo_4 # return
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LBB_foo_1: # no_exit.preheader
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xorl %ecx, %ecx
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LBB_foo_2: # no_exit
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movl L_X$non_lazy_ptr, %edx
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movl %ecx, (%edx)
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incl %ecx
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cmpl %eax, %ecx
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jne LBB_foo_2 # no_exit
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LBB_foo_3: # return.loopexit
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LBB_foo_4: # return
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ret
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We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
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remateralization is implemented. This can be accomplished with 1) a target
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dependent LICM pass or 2) makeing SelectDAG represent the whole function.
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//===---------------------------------------------------------------------===//
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The following tests perform worse with LSR:
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lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
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//===---------------------------------------------------------------------===//
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Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
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FR64 to VR128.
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//===---------------------------------------------------------------------===//
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mov $reg, 48(%esp)
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...
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leal 48(%esp), %eax
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mov %eax, (%esp)
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call _foo
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Obviously it would have been better for the first mov (or any op) to store
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directly %esp[0] if there are no other uses.
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//===---------------------------------------------------------------------===//
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Adding to the list of cmp / test poor codegen issues:
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int test(__m128 *A, __m128 *B) {
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if (_mm_comige_ss(*A, *B))
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return 3;
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else
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return 4;
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}
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_test:
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movl 8(%esp), %eax
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movaps (%eax), %xmm0
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movl 4(%esp), %eax
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movaps (%eax), %xmm1
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comiss %xmm0, %xmm1
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setae %al
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movzbl %al, %ecx
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movl $3, %eax
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movl $4, %edx
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cmpl $0, %ecx
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cmove %edx, %eax
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ret
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Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
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are a number of issues. 1) We are introducing a setcc between the result of the
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intrisic call and select. 2) The intrinsic is expected to produce a i32 value
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so a any extend (which becomes a zero extend) is added.
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We probably need some kind of target DAG combine hook to fix this.
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//===---------------------------------------------------------------------===//
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We generate significantly worse code for this than GCC:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
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http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
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There is also one case we do worse on PPC.
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//===---------------------------------------------------------------------===//
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If shorter, we should use things like:
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movzwl %ax, %eax
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instead of:
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andl $65535, %EAX
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The former can also be used when the two-addressy nature of the 'and' would
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require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
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//===---------------------------------------------------------------------===//
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Bad codegen:
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char foo(int x) { return x; }
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_foo:
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movl 4(%esp), %eax
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shll $24, %eax
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sarl $24, %eax
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ret
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SIGN_EXTEND_INREG can be implemented as (sext (trunc)) to take advantage of
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sub-registers.
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//===---------------------------------------------------------------------===//
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Consider this:
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typedef struct pair { float A, B; } pair;
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void pairtest(pair P, float *FP) {
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*FP = P.A+P.B;
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}
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We currently generate this code with llvmgcc4:
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_pairtest:
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subl $12, %esp
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movl 20(%esp), %eax
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movl %eax, 4(%esp)
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movl 16(%esp), %eax
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movl %eax, (%esp)
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movss (%esp), %xmm0
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addss 4(%esp), %xmm0
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movl 24(%esp), %eax
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movss %xmm0, (%eax)
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addl $12, %esp
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ret
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we should be able to generate:
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_pairtest:
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movss 4(%esp), %xmm0
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movl 12(%esp), %eax
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addss 8(%esp), %xmm0
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movss %xmm0, (%eax)
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ret
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The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
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integer chunks. It does this so that structs like {short,short} are passed in
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a single 32-bit integer stack slot. We should handle the safe cases above much
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nicer, while still handling the hard cases.
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//===---------------------------------------------------------------------===//
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Another instruction selector deficiency:
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void %bar() {
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%tmp = load int (int)** %foo
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%tmp = tail call int %tmp( int 3 )
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ret void
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}
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_bar:
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subl $12, %esp
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movl L_foo$non_lazy_ptr, %eax
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movl (%eax), %eax
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call *%eax
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addl $12, %esp
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ret
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The current isel scheme will not allow the load to be folded in the call since
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the load's chain result is read by the callseq_start.
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//===---------------------------------------------------------------------===//
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Don't forget to find a way to squash noop truncates in the JIT environment.
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//===---------------------------------------------------------------------===//
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Implement anyext in the same manner as truncate that would allow them to be
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eliminated.
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//===---------------------------------------------------------------------===//
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How about implementing truncate / anyext as a property of machine instruction
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operand? i.e. Print as 32-bit super-class register / 16-bit sub-class register.
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Do this for the cases where a truncate / anyext is guaranteed to be eliminated.
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For IA32 that is truncate from 32 to 16 and anyext from 16 to 32.
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//===---------------------------------------------------------------------===//
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For this:
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int test(int a)
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{
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return a * 3;
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}
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We currently emits
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imull $3, 4(%esp), %eax
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Perhaps this is what we really should generate is? Is imull three or four
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cycles? Note: ICC generates this:
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movl 4(%esp), %eax
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leal (%eax,%eax,2), %eax
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The current instruction priority is based on pattern complexity. The former is
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more "complex" because it folds a load so the latter will not be emitted.
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Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
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should always try to match LEA first since the LEA matching code does some
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estimate to determine whether the match is profitable.
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However, if we care more about code size, then imull is better. It's two bytes
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shorter than movl + leal.
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//===---------------------------------------------------------------------===//
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Implement CTTZ, CTLZ with bsf and bsr.
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//===---------------------------------------------------------------------===//
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It appears gcc place string data with linkonce linkage in
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.section __TEXT,__const_coal,coalesced instead of
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.section __DATA,__const_coal,coalesced.
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Take a look at darwin.h, there are other Darwin assembler directives that we
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do not make use of.
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//===---------------------------------------------------------------------===//
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We should handle __attribute__ ((__visibility__ ("hidden"))).
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//===---------------------------------------------------------------------===//
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int %foo(int* %a, int %t) {
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entry:
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br label %cond_true
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cond_true: ; preds = %cond_true, %entry
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%x.0.0 = phi int [ 0, %entry ], [ %tmp9, %cond_true ]
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%t_addr.0.0 = phi int [ %t, %entry ], [ %tmp7, %cond_true ]
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%tmp2 = getelementptr int* %a, int %x.0.0
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%tmp3 = load int* %tmp2 ; <int> [#uses=1]
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%tmp5 = add int %t_addr.0.0, %x.0.0 ; <int> [#uses=1]
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%tmp7 = add int %tmp5, %tmp3 ; <int> [#uses=2]
|
|
%tmp9 = add int %x.0.0, 1 ; <int> [#uses=2]
|
|
%tmp = setgt int %tmp9, 39 ; <bool> [#uses=1]
|
|
br bool %tmp, label %bb12, label %cond_true
|
|
|
|
bb12: ; preds = %cond_true
|
|
ret int %tmp7
|
|
}
|
|
|
|
is pessimized by -loop-reduce and -indvars
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Use cpuid to auto-detect CPU features such as SSE, SSE2, and SSE3.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
u32 to float conversion improvement:
|
|
|
|
float uint32_2_float( unsigned u ) {
|
|
float fl = (int) (u & 0xffff);
|
|
float fh = (int) (u >> 16);
|
|
fh *= 0x1.0p16f;
|
|
return fh + fl;
|
|
}
|
|
|
|
00000000 subl $0x04,%esp
|
|
00000003 movl 0x08(%esp,1),%eax
|
|
00000007 movl %eax,%ecx
|
|
00000009 shrl $0x10,%ecx
|
|
0000000c cvtsi2ss %ecx,%xmm0
|
|
00000010 andl $0x0000ffff,%eax
|
|
00000015 cvtsi2ss %eax,%xmm1
|
|
00000019 mulss 0x00000078,%xmm0
|
|
00000021 addss %xmm1,%xmm0
|
|
00000025 movss %xmm0,(%esp,1)
|
|
0000002a flds (%esp,1)
|
|
0000002d addl $0x04,%esp
|
|
00000030 ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
When using fastcc abi, align stack slot of argument of type double on 8 byte
|
|
boundary to improve performance.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Codegen:
|
|
|
|
int f(int a, int b) {
|
|
if (a == 4 || a == 6)
|
|
b++;
|
|
return b;
|
|
}
|
|
|
|
|
|
as:
|
|
|
|
or eax, 2
|
|
cmp eax, 6
|
|
jz label
|
|
|
|
If we aren't going to do this, we should lower the switch better. We compile
|
|
the code to:
|
|
|
|
_f:
|
|
movl 8(%esp), %eax
|
|
movl 4(%esp), %ecx
|
|
cmpl $6, %ecx
|
|
jl LBB1_4 #entry
|
|
jmp LBB1_3 #entry
|
|
LBB1_3: #entry
|
|
cmpl $6, %ecx
|
|
je LBB1_1 #bb
|
|
jmp LBB1_2 #UnifiedReturnBlock
|
|
LBB1_4: #entry
|
|
cmpl $4, %ecx
|
|
jne LBB1_2 #UnifiedReturnBlock
|
|
LBB1_1: #bb
|
|
incl %eax
|
|
ret
|
|
LBB1_2: #UnifiedReturnBlock
|
|
ret
|
|
|
|
In the code above, the 'if' is turned into a 'switch' at the mid-level. It
|
|
looks like the 'lower to branches' mode could be improved a little here. In
|
|
particular, the fall-through to LBB1_3 doesn't need a branch. It would also be
|
|
nice to eliminate the redundant "cmp 6", maybe by lowering to a linear sequence
|
|
of compares if there are below a certain number of cases (instead of a binary
|
|
sequence)?
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Compile:
|
|
int %test(ulong *%tmp) {
|
|
%tmp = load ulong* %tmp ; <ulong> [#uses=1]
|
|
%tmp.mask = shr ulong %tmp, ubyte 50 ; <ulong> [#uses=1]
|
|
%tmp.mask = cast ulong %tmp.mask to ubyte
|
|
%tmp2 = and ubyte %tmp.mask, 3 ; <ubyte> [#uses=1]
|
|
%tmp2 = cast ubyte %tmp2 to int ; <int> [#uses=1]
|
|
ret int %tmp2
|
|
}
|
|
|
|
to:
|
|
|
|
_test:
|
|
movl 4(%esp), %eax
|
|
movl 4(%eax), %eax
|
|
shrl $18, %eax
|
|
andl $3, %eax
|
|
ret
|
|
|
|
instead of:
|
|
|
|
_test:
|
|
movl 4(%esp), %eax
|
|
movl 4(%eax), %eax
|
|
shrl $18, %eax
|
|
# TRUNCATE movb %al, %al
|
|
andb $3, %al
|
|
movzbl %al, %eax
|
|
ret
|
|
|
|
This saves a movzbl, and saves a truncate if it doesn't get coallesced right.
|
|
This is a simple DAGCombine to propagate the zext through the and.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
|
|
simplifications for integer "x cmp y ? a : b". For example, instead of:
|
|
|
|
int G;
|
|
void f(int X, int Y) {
|
|
G = X < 0 ? 14 : 13;
|
|
}
|
|
|
|
compiling to:
|
|
|
|
_f:
|
|
movl $14, %eax
|
|
movl $13, %ecx
|
|
movl 4(%esp), %edx
|
|
testl %edx, %edx
|
|
cmovl %eax, %ecx
|
|
movl %ecx, _G
|
|
ret
|
|
|
|
it could be:
|
|
_f:
|
|
movl 4(%esp), %eax
|
|
sarl $31, %eax
|
|
notl %eax
|
|
addl $14, %eax
|
|
movl %eax, _G
|
|
ret
|
|
|
|
etc.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Currently we don't have elimination of redundant stack manipulations. Consider
|
|
the code:
|
|
|
|
int %main() {
|
|
entry:
|
|
call fastcc void %test1( )
|
|
call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
|
|
ret int 0
|
|
}
|
|
|
|
declare fastcc void %test1()
|
|
|
|
declare fastcc void %test2(sbyte*)
|
|
|
|
|
|
This currently compiles to:
|
|
|
|
subl $16, %esp
|
|
call _test5
|
|
addl $12, %esp
|
|
subl $16, %esp
|
|
movl $_test5, (%esp)
|
|
call _test6
|
|
addl $12, %esp
|
|
|
|
The add\sub pair is really unneeded here.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We generate really bad code in some cases due to lowering SETCC/SELECT at
|
|
legalize time, which prevents the post-legalize dag combine pass from
|
|
understanding the code. As a silly example, this prevents us from folding
|
|
stuff like this:
|
|
|
|
bool %test(ulong %x) {
|
|
%tmp = setlt ulong %x, 4294967296
|
|
ret bool %tmp
|
|
}
|
|
|
|
into x.h == 0
|
|
|
|
|