Evan Cheng 61230d18d2 Try schedule def + use closer whne Sethi-Ullman numbers are the same. ... e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35089 91177308-0d34-0410-b5e6-96231b3b80d8		2007-03-13 23:25:11 +00:00
..
CallingConvLower.cpp	add methods for analysis of call results and return nodes.	2007-02-28 07:09:40 +00:00
DAGCombiner.cpp	Avoid combining indexed load further.	2007-03-07 08:07:03 +00:00
LegalizeDAG.cpp	Refactoring of formal parameter flags. Enable properly use of	2007-03-07 16:25:09 +00:00
Makefile	For PR780:	2006-07-26 16:18:00 +00:00
ScheduleDAG.cpp	print target nodes nicely	2007-02-17 06:38:37 +00:00
ScheduleDAGList.cpp	switch the sched unit map over to use a DenseMap instead of std::map. This	2007-02-03 01:34:13 +00:00
ScheduleDAGRRList.cpp	Try schedule def + use closer whne Sethi-Ullman numbers are the same.	2007-03-13 23:25:11 +00:00
ScheduleDAGSimple.cpp	switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This	2007-02-04 08:47:20 +00:00
SelectionDAG.cpp	fold away addc nodes when we know there cannot be a carry-out.	2007-03-04 20:40:38 +00:00
SelectionDAGISel.cpp	implement support for floating point constants used as inline asm memory operands.	2007-03-08 22:29:47 +00:00
SelectionDAGPrinter.cpp	Removing even more <iostream> includes.	2006-12-07 20:04:42 +00:00
TargetLowering.cpp	More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.	2007-03-12 23:37:10 +00:00