llvm-6502/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
Tim Northover ca396e391e IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:

	cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 10:48:52 +00:00

27 lines
883 B
LLVM

; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin | FileCheck %s
; PR8297
;
; On i386, i64 cmpxchg is lowered during legalize types to extract the
; 64-bit result into a pair of fixed regs. So creation of the DAG node
; happens in a different place. See
; X86TargetLowering::ReplaceNodeResults, case ATOMIC_CMP_SWAP.
;
; Neither Atomic-xx.ll nor atomic_op.ll cover this. Those tests were
; autogenerated from C source before 64-bit variants were supported.
;
; Note that this case requires a loop around the cmpxchg to force
; machine licm to query alias anlysis, exposing a bad
; MachineMemOperand.
define void @foo(i64* %ptr) nounwind inlinehint {
entry:
br label %loop
loop:
; CHECK: lock
; CHECK-NEXT: cmpxchg8b
%r = cmpxchg i64* %ptr, i64 0, i64 1 monotonic monotonic
%stored1 = icmp eq i64 %r, 0
br i1 %stored1, label %loop, label %continue
continue:
ret void
}