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https://github.com/c64scene-ar/llvm-6502.git
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3957d4245f
This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to MVT::v8i8 (and vice versa). This patch extends the logic from revision 208107 to also handle MVT::v4i16 and MVT::v8i8. Also, this patch correctly propagates Undef values when performing the widening of a vector (example: when widening from v2i32 to v4i32, the upper 64bits of the resulting vector are 'undef'). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209451 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
3.8 KiB
LLVM
156 lines
3.8 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 -mattr=+sse2 | FileCheck %s
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define double @test1(double %A) {
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%1 = bitcast double %A to <2 x i32>
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%add = add <2 x i32> %1, <i32 3, i32 5>
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%2 = bitcast <2 x i32> %add to double
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ret double %2
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}
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; FIXME: Ideally we should be able to fold the entire body of @test1 into a
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; single paddd instruction. At the moment we produce the sequence
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; pshufd+paddq+pshufd.
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; CHECK-LABEL: test1
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; CHECK-NOT: movsd
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; CHECK: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define double @test2(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%add = add <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %add to double
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ret double %3
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}
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; FIXME: Ideally we should be able to fold the entire body of @test2 into a
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; single 'paddd %xmm1, %xmm0' instruction. At the moment we produce the
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; sequence pshufd+pshufd+paddq+pshufd.
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; CHECK-LABEL: test2
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; CHECK-NOT: movsd
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; CHECK: pshufd
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define i64 @test3(i64 %A) {
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%1 = bitcast i64 %A to <2 x float>
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%add = fadd <2 x float> %1, <float 3.0, float 5.0>
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%2 = bitcast <2 x float> %add to i64
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ret i64 %2
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: pshufd
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; CHECK: addps
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; CHECK-NOT: pshufd
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; CHECK: ret
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define i64 @test4(i64 %A) {
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%1 = bitcast i64 %A to <2 x i32>
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%add = add <2 x i32> %1, <i32 3, i32 5>
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%2 = bitcast <2 x i32> %add to i64
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ret i64 %2
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}
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; FIXME: At the moment we still produce the sequence pshufd+paddq+pshufd.
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; Ideally, we should fold that sequence into a single paddd.
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; CHECK-LABEL: test4
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; CHECK: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: pshufd
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; CHECK: ret
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define double @test5(double %A) {
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%1 = bitcast double %A to <2 x float>
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%add = fadd <2 x float> %1, <float 3.0, float 5.0>
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%2 = bitcast <2 x float> %add to double
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ret double %2
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}
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; CHECK-LABEL: test5
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; CHECK: addps
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; CHECK-NEXT: ret
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define double @test6(double %A) {
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%1 = bitcast double %A to <4 x i16>
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%add = add <4 x i16> %1, <i16 3, i16 4, i16 5, i16 6>
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%2 = bitcast <4 x i16> %add to double
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ret double %2
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}
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; FIXME: Ideally we should be able to fold the entire body of @test6 into a
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; single paddw instruction.
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; CHECK-LABEL: test6
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; CHECK-NOT: movsd
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; CHECK: punpcklwd
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; CHECK-NEXT: paddd
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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define double @test7(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%add = add <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %add to double
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ret double %3
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}
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; FIXME: Ideally we should be able to fold the entire body of @test7 into a
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; single 'paddw %xmm1, %xmm0' instruction. At the moment we produce the
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; sequence pshufd+pshufd+paddd+pshufd.
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; CHECK-LABEL: test7
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; CHECK-NOT: movsd
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; CHECK: punpcklwd
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; CHECK-NEXT: punpcklwd
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; CHECK-NEXT: paddd
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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define double @test8(double %A) {
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%1 = bitcast double %A to <8 x i8>
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%add = add <8 x i8> %1, <i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10>
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%2 = bitcast <8 x i8> %add to double
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ret double %2
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}
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; FIXME: Ideally we should be able to fold the entire body of @test8 into a
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; single paddb instruction. At the moment we produce the sequence
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; pshufd+paddw+pshufd.
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; CHECK-LABEL: test8
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; CHECK-NOT: movsd
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; CHECK: punpcklbw
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; CHECK-NEXT: paddw
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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define double @test9(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%add = add <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %add to double
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ret double %3
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}
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; FIXME: Ideally we should be able to fold the entire body of @test9 into a
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; single 'paddb %xmm1, %xmm0' instruction. At the moment we produce the
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; sequence pshufd+pshufd+paddw+pshufd.
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; CHECK-LABEL: test9
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; CHECK-NOT: movsd
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; CHECK: punpcklbw
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; CHECK-NEXT: punpcklbw
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; CHECK-NEXT: paddw
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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