Andrew Trick 614dacc910 RegisterPressure heuristics currently require signed comparisons. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8

2013-04-05 00:31:34 +00:00

..

AArch64

Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings

2013-03-26 18:56:54 +00:00

ARM

Avoid high-latency false CPSR dependencies even for tMOVSi.

2013-04-04 18:25:36 +00:00

CPP

test commit: remove blank line.

2013-03-14 05:43:59 +00:00

Generic

XFAIL some of the generic CodeGen tests for Hexagon.

2013-03-25 21:04:16 +00:00

Hexagon

Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.

2013-03-28 19:34:49 +00:00

Inputs

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

MBlaze

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

Mips

[mips] Small update to the implementation of eh.return for Mips.

2013-04-02 23:02:07 +00:00

MSP430

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

NVPTX

[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.

2013-03-30 14:29:30 +00:00

PowerPC

PPC: Improve code generation for mixed-precision reciprocal sqrt

2013-04-04 22:44:12 +00:00

R600

R600: Take export into account when computing cf address

2013-04-04 13:59:59 +00:00

SI

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SPARC

Add SPARC v9 support for select on 64-bit compares.

2013-04-04 03:08:00 +00:00

Thumb

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

Thumb2

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X86

RegisterPressure heuristics currently require signed comparisons.

2013-04-05 00:31:34 +00:00

XCore

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00