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e0de44adba
We will decide with subtarget support whether we ever use an i64 register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23734 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
1.3 KiB
TableGen
38 lines
1.3 KiB
TableGen
//===- PPC32.td - Describe the PowerPC Target Machine ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "PowerPCRegisterInfo.td"
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include "PowerPCInstrInfo.td"
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def PPC32 : Target {
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// Pointers on PPC32 are 32-bits in size.
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let PointerType = i32;
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// According to the Mach-O Runtime ABI, these regs are nonvolatile across
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// calls
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let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
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F30, F31, CR2, CR3, CR4, LR];
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// Pull in Instruction Info:
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let InstructionSet = PowerPCInstrInfo;
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}
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