mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-10 17:29:44 +00:00
c2884320fe
This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
2.5 KiB
TableGen
75 lines
2.5 KiB
TableGen
//===- AArch64.td - Describe the AArch64 Target Machine -------*- tblgen -*-==//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This is the top level entry point for the AArch64 target.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// AArch64 Subtarget features.
|
|
//
|
|
|
|
def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
|
|
"Enable ARMv8 FP">;
|
|
|
|
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
|
|
"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
|
|
|
|
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
|
|
"Enable cryptographic instructions">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// AArch64 Processors
|
|
//
|
|
|
|
include "AArch64Schedule.td"
|
|
|
|
def : Processor<"generic", GenericItineraries,
|
|
[FeatureFPARMv8, FeatureNEON, FeatureCrypto]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AArch64RegisterInfo.td"
|
|
|
|
include "AArch64CallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AArch64InstrInfo.td"
|
|
|
|
def AArch64InstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly printer
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def A64InstPrinter : AsmWriter {
|
|
string AsmWriterClassName = "InstPrinter";
|
|
bit isMCAsmWriter = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declare the target which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def AArch64 : Target {
|
|
let InstructionSet = AArch64InstrInfo;
|
|
let AssemblyWriters = [A64InstPrinter];
|
|
}
|