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9d547b618c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228316 91177308-0d34-0410-b5e6-96231b3b80d8
66 lines
2.6 KiB
TableGen
66 lines
2.6 KiB
TableGen
//===- HexagonInstrInfoVector.td - Hexagon Vector Patterns -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon Vector instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
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def V4I1: PatLeaf<(v4i1 PredRegs:$R)>;
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def V8I1: PatLeaf<(v8i1 PredRegs:$R)>;
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def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
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def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
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def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
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def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>;
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def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
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// Vector shift support. Vector shifting in Hexagon is rather different
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// from internal representation of LLVM.
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// LLVM assumes all shifts (in vector case) will have the form
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// <VT> = SHL/SRA/SRL <VT> by <VT>
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// while Hexagon has the following format:
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// <VT> = SHL/SRA/SRL <VT> by <IT/i32>
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// As a result, special care is needed to guarantee correctness and
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// performance.
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class vshift_v4i16<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
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: S_2OpInstImm<Str, MajOp, MinOp, u4Imm,
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[(set (v4i16 DoubleRegs:$dst),
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(Op (v4i16 DoubleRegs:$src1), u4ImmPred:$src2))]> {
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bits<4> src2;
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let Inst{11-8} = src2;
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}
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class vshift_v2i32<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
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: S_2OpInstImm<Str, MajOp, MinOp, u5Imm,
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[(set (v2i32 DoubleRegs:$dst),
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(Op (v2i32 DoubleRegs:$src1), u5ImmPred:$src2))]> {
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bits<5> src2;
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let Inst{12-8} = src2;
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}
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def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>;
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def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>;
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def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>;
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def S2_asr_i_vh : vshift_v4i16<sra, "vasrh", 0b100, 0b000>;
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def S2_lsr_i_vh : vshift_v4i16<srl, "vlsrh", 0b100, 0b001>;
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def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>;
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// Vector shift words by register
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def S2_asr_r_vw : T_S3op_shiftVect < "vasrw", 0b00, 0b00>;
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def S2_lsr_r_vw : T_S3op_shiftVect < "vlsrw", 0b00, 0b01>;
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def S2_asl_r_vw : T_S3op_shiftVect < "vaslw", 0b00, 0b10>;
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def S2_lsl_r_vw : T_S3op_shiftVect < "vlslw", 0b00, 0b11>;
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// Vector shift halfwords by register
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def S2_asr_r_vh : T_S3op_shiftVect < "vasrh", 0b01, 0b00>;
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def S2_lsr_r_vh : T_S3op_shiftVect < "vlsrh", 0b01, 0b01>;
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def S2_asl_r_vh : T_S3op_shiftVect < "vaslh", 0b01, 0b10>;
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def S2_lsl_r_vh : T_S3op_shiftVect < "vlslh", 0b01, 0b11>;
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