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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
914 B
LLVM
26 lines
914 B
LLVM
; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
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; fixed, the movb should go away as well.
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; RUN: llc < %s -march=x86 -relocation-model=static | \
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; RUN: grep movl
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@B = external global i32 ; <i32*> [#uses=2]
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@C = external global i16* ; <i16**> [#uses=2]
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define void @test(i32 %A) {
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%A.upgrd.1 = trunc i32 %A to i8 ; <i8> [#uses=1]
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%tmp2 = load i32, i32* @B ; <i32> [#uses=1]
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%tmp3 = and i8 %A.upgrd.1, 16 ; <i8> [#uses=1]
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%shift.upgrd.2 = zext i8 %tmp3 to i32 ; <i32> [#uses=1]
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%tmp4 = shl i32 %tmp2, %shift.upgrd.2 ; <i32> [#uses=1]
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store i32 %tmp4, i32* @B
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%tmp6 = lshr i32 %A, 3 ; <i32> [#uses=1]
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%tmp = load i16*, i16** @C ; <i16*> [#uses=1]
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%tmp8 = ptrtoint i16* %tmp to i32 ; <i32> [#uses=1]
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%tmp9 = add i32 %tmp8, %tmp6 ; <i32> [#uses=1]
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%tmp9.upgrd.3 = inttoptr i32 %tmp9 to i16* ; <i16*> [#uses=1]
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store i16* %tmp9.upgrd.3, i16** @C
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ret void
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}
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