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https://github.com/c64scene-ar/llvm-6502.git
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2fbfdcffd3
class. The Method class is obsolete (renamed) and all references to it are being converted over to Function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2144 91177308-0d34-0410-b5e6-96231b3b80d8
312 lines
12 KiB
C++
312 lines
12 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// SparcInstrInfo.cpp
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//
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// Purpose:
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//
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// History:
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// 10/15/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "SparcInternals.h"
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#include "SparcInstrSelectionSupport.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/Function.h"
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#include "llvm/ConstantVals.h"
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#include "llvm/DerivedTypes.h"
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//************************ Internal Functions ******************************/
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static inline MachineInstr*
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CreateIntSetInstruction(int64_t C, Value* dest,
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std::vector<TmpInstruction*>& tempVec)
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{
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MachineInstr* minstr;
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uint64_t absC = (C >= 0)? C : -C;
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if (absC > (unsigned int) ~0)
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{ // C does not fit in 32 bits
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TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
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tempVec.push_back(tmpReg);
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minstr = new MachineInstr(SETX);
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minstr->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed, C);
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minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpReg,
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/*isdef*/ true);
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minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
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}
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else
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{
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minstr = new MachineInstr(SETSW);
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minstr->SetMachineOperandConst(0,MachineOperand::MO_SignExtendedImmed,C);
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minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
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}
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return minstr;
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}
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static inline MachineInstr*
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CreateUIntSetInstruction(uint64_t C, Value* dest,
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std::vector<TmpInstruction*>& tempVec)
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{
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MachineInstr* minstr;
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if (C > (unsigned int) ~0)
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{ // C does not fit in 32 bits
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assert(dest->getType() == Type::ULongTy && "Sign extension problems");
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TmpInstruction *tmpReg = new TmpInstruction(Type::IntTy);
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tempVec.push_back(tmpReg);
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minstr = new MachineInstr(SETX);
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minstr->SetMachineOperandConst(0,MachineOperand::MO_SignExtendedImmed,C);
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minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
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tmpReg, /*isdef*/ true);
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minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
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}
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else if (dest->getType() == Type::ULongTy)
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{
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minstr = new MachineInstr(SETUW);
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minstr->SetMachineOperandConst(0, MachineOperand::MO_UnextendedImmed, C);
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minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
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}
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else
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{ // cast to signed type of the right length and use signed op (SETSW)
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// to get correct sign extension
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//
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minstr = new MachineInstr(SETSW);
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minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
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switch (dest->getType()->getPrimitiveID())
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{
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case Type::UIntTyID:
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minstr->SetMachineOperandConst(0,
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MachineOperand::MO_SignExtendedImmed,
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(int) C);
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break;
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case Type::UShortTyID:
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minstr->SetMachineOperandConst(0,
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MachineOperand::MO_SignExtendedImmed,
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(short) C);
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break;
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case Type::UByteTyID:
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minstr->SetMachineOperandConst(0,
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MachineOperand::MO_SignExtendedImmed,
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(char) C);
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break;
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default:
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assert(0 && "Unexpected unsigned type");
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break;
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}
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}
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return minstr;
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}
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//************************* External Classes *******************************/
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class MachineInstrInfo.
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//---------------------------------------------------------------------------
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/*ctor*/
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UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
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: MachineInstrInfo(tgt, SparcMachineInstrDesc,
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/*descSize = */ NUM_TOTAL_OPCODES,
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/*numRealOpCodes = */ NUM_REAL_OPCODES)
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{
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}
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//
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `minstrVec'.
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// Any temp. registers (TmpInstruction) created are returned in `tempVec'.
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//
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void
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UltraSparcInstrInfo::CreateCodeToLoadConst(Function *F, Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>&minstrVec,
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std::vector<TmpInstruction*>& tempVec) const
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{
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MachineInstr* minstr;
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assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
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"I only know about constant values and global addresses");
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// Use a "set" instruction for known constants that can go in an integer reg.
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// Use a "load" instruction for all other constants, in particular,
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// floating point constants and addresses of globals.
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//
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const Type* valType = val->getType();
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if (valType->isIntegral() || valType == Type::BoolTy)
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{
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if (ConstantUInt* uval = dyn_cast<ConstantUInt>(val))
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{
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uint64_t C = uval->getValue();
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minstr = CreateUIntSetInstruction(C, dest, tempVec);
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}
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else
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{
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bool isValidConstant;
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int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
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assert(isValidConstant && "Unrecognized constant");
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minstr = CreateIntSetInstruction(C, dest, tempVec);
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}
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minstrVec.push_back(minstr);
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}
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else
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{
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// Make an instruction sequence to load the constant, viz:
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// SETX <addr-of-constant>, tmpReg, addrReg
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// LOAD /*addr*/ addrReg, /*offset*/ 0, dest
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// Only the SETX is needed if `val' is a GlobalValue, i.e,. it is
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// itself a constant address. Otherwise, both are needed.
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Value* addrVal;
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int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
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TmpInstruction* tmpReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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tempVec.push_back(tmpReg);
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if (isa<Constant>(val))
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{
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// Create another TmpInstruction for the hidden integer register
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TmpInstruction* addrReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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tempVec.push_back(addrReg);
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addrVal = addrReg;
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}
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else
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addrVal = dest;
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minstr = new MachineInstr(SETX);
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minstr->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, val);
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minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,tmpReg,
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/*isdef*/ true);
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minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
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addrVal);
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minstrVec.push_back(minstr);
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if (isa<Constant>(val))
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{
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// Make sure constant is emitted to constant pool in assembly code.
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MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
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mcinfo.addToConstantPool(cast<Constant>(val));
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// Generate the load instruction
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minstr = new MachineInstr(ChooseLoadInstruction(val->getType()));
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minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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addrVal);
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minstr->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
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zeroOffset);
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minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
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dest);
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minstrVec.push_back(minstr);
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}
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}
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}
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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// The generated instructions are returned in `minstrVec'.
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// Any temp. registers (TmpInstruction) created are returned in `tempVec'.
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//
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void
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UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(Function *F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& minstrVec,
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std::vector<TmpInstruction*>& tempVec,
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TargetMachine& target) const
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{
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assert((val->getType()->isIntegral() || val->getType()->isPointerType())
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&& "Source type must be integral");
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assert((dest->getType() == Type::FloatTy || dest->getType() == Type::DoubleTy)
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&& "Dest type must be float/double");
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MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
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int offset = mcinfo.allocateLocalVar(target, val);
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// Store instruction stores `val' to [%fp+offset].
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// The store and load opCodes are based on the value being copied, and
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// they use integer and float types that accomodate the
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// larger of the source type and the destination type:
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// On SparcV9: int for float, long for double.
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//
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Type* tmpType = (dest->getType() == Type::FloatTy)? Type::IntTy
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: Type::LongTy;
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MachineInstr* store = new MachineInstr(ChooseStoreInstruction(tmpType));
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store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
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store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
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store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed, offset);
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minstrVec.push_back(store);
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// Load instruction loads [%fp+offset] to `dest'.
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//
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MachineInstr* load =new MachineInstr(ChooseLoadInstruction(dest->getType()));
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load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
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load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
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load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
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minstrVec.push_back(load);
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}
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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// See the previous function for information about return values.
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//
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void
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UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(Function *F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& minstrVec,
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std::vector<TmpInstruction*>& tempVec,
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TargetMachine& target) const
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{
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assert((val->getType() ==Type::FloatTy || val->getType() ==Type::DoubleTy)
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&& "Source type must be float/double");
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assert((dest->getType()->isIntegral() || dest->getType()->isPointerType())
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&& "Dest type must be integral");
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MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
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int offset = mcinfo.allocateLocalVar(target, val);
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// Store instruction stores `val' to [%fp+offset].
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// The store and load opCodes are based on the value being copied, and
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// they use the integer type that matches the source type in size:
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// On SparcV9: int for float, long for double.
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//
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Type* tmpType = (val->getType() == Type::FloatTy)? Type::IntTy
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: Type::LongTy;
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MachineInstr* store=new MachineInstr(ChooseStoreInstruction(val->getType()));
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store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
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store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
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store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
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minstrVec.push_back(store);
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// Load instruction loads [%fp+offset] to `dest'.
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//
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MachineInstr* load = new MachineInstr(ChooseLoadInstruction(tmpType));
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load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
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load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed, offset);
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load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
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minstrVec.push_back(load);
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}
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