mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
263 lines
5.2 KiB
LLVM
263 lines
5.2 KiB
LLVM
; RUN: llc < %s -march=arm64 -asm-verbose=false | FileCheck %s
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define i32 @t1(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: add w0, w1, w0
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; CHECK: ret
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%add = add i32 %b, %a
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ret i32 %add
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}
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define i32 @t2(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: udiv w0, w0, w1
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; CHECK: ret
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%udiv = udiv i32 %a, %b
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ret i32 %udiv
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}
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define i64 @t3(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: udiv x0, x0, x1
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; CHECK: ret
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%udiv = udiv i64 %a, %b
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ret i64 %udiv
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}
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define i32 @t4(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: sdiv w0, w0, w1
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; CHECK: ret
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%sdiv = sdiv i32 %a, %b
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ret i32 %sdiv
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}
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define i64 @t5(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: sdiv x0, x0, x1
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; CHECK: ret
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%sdiv = sdiv i64 %a, %b
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ret i64 %sdiv
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}
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define i32 @t6(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: lslv w0, w0, w1
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; CHECK: ret
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%shl = shl i32 %a, %b
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ret i32 %shl
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}
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define i64 @t7(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t7:
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; CHECK: lslv x0, x0, x1
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; CHECK: ret
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%shl = shl i64 %a, %b
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ret i64 %shl
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}
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define i32 @t8(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t8:
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; CHECK: lsrv w0, w0, w1
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; CHECK: ret
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%lshr = lshr i32 %a, %b
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ret i32 %lshr
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}
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define i64 @t9(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t9:
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; CHECK: lsrv x0, x0, x1
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; CHECK: ret
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%lshr = lshr i64 %a, %b
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ret i64 %lshr
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}
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define i32 @t10(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t10:
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; CHECK: asrv w0, w0, w1
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; CHECK: ret
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%ashr = ashr i32 %a, %b
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ret i32 %ashr
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}
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define i64 @t11(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t11:
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; CHECK: asrv x0, x0, x1
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; CHECK: ret
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%ashr = ashr i64 %a, %b
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ret i64 %ashr
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}
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define i32 @t12(i16 %a, i32 %x) nounwind ssp {
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entry:
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; CHECK-LABEL: t12:
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; CHECK: add w0, w1, w0, sxth
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; CHECK: ret
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%c = sext i16 %a to i32
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%e = add i32 %x, %c
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ret i32 %e
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}
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define i32 @t13(i16 %a, i32 %x) nounwind ssp {
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entry:
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; CHECK-LABEL: t13:
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; CHECK: add w0, w1, w0, sxth #2
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; CHECK: ret
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%c = sext i16 %a to i32
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%d = shl i32 %c, 2
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%e = add i32 %x, %d
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ret i32 %e
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}
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define i64 @t14(i16 %a, i64 %x) nounwind ssp {
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entry:
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; CHECK-LABEL: t14:
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; CHECK: add x0, x1, w0, uxth #3
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; CHECK: ret
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%c = zext i16 %a to i64
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%d = shl i64 %c, 3
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%e = add i64 %x, %d
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ret i64 %e
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}
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; rdar://9160598
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define i64 @t15(i64 %a, i64 %x) nounwind ssp {
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entry:
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; CHECK-LABEL: t15:
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; CHECK: add x0, x1, w0, uxtw
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; CHECK: ret
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%b = and i64 %a, 4294967295
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%c = add i64 %x, %b
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ret i64 %c
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}
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define i64 @t16(i64 %x) nounwind ssp {
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entry:
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; CHECK-LABEL: t16:
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; CHECK: lsl x0, x0, #1
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; CHECK: ret
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%a = shl i64 %x, 1
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ret i64 %a
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}
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; rdar://9166974
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define i64 @t17(i16 %a, i64 %x) nounwind ssp {
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entry:
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; CHECK-LABEL: t17:
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; CHECK: sxth [[REG:x[0-9]+]], x0
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; CHECK: sub x0, xzr, [[REG]], lsl #32
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; CHECK: ret
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%tmp16 = sext i16 %a to i64
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%tmp17 = mul i64 %tmp16, -4294967296
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ret i64 %tmp17
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}
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define i32 @t18(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t18:
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; CHECK: sdiv w0, w0, w1
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; CHECK: ret
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%sdiv = call i32 @llvm.arm64.sdiv.i32(i32 %a, i32 %b)
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ret i32 %sdiv
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}
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define i64 @t19(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t19:
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; CHECK: sdiv x0, x0, x1
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; CHECK: ret
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%sdiv = call i64 @llvm.arm64.sdiv.i64(i64 %a, i64 %b)
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ret i64 %sdiv
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}
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define i32 @t20(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t20:
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; CHECK: udiv w0, w0, w1
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; CHECK: ret
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%udiv = call i32 @llvm.arm64.udiv.i32(i32 %a, i32 %b)
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ret i32 %udiv
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}
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define i64 @t21(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t21:
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; CHECK: udiv x0, x0, x1
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; CHECK: ret
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%udiv = call i64 @llvm.arm64.udiv.i64(i64 %a, i64 %b)
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ret i64 %udiv
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}
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declare i32 @llvm.arm64.sdiv.i32(i32, i32) nounwind readnone
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declare i64 @llvm.arm64.sdiv.i64(i64, i64) nounwind readnone
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declare i32 @llvm.arm64.udiv.i32(i32, i32) nounwind readnone
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declare i64 @llvm.arm64.udiv.i64(i64, i64) nounwind readnone
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; 32-bit not.
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define i32 @inv_32(i32 %x) nounwind ssp {
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entry:
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; CHECK: inv_32
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; CHECK: mvn w0, w0
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; CHECK: ret
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%inv = xor i32 %x, -1
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ret i32 %inv
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}
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; 64-bit not.
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define i64 @inv_64(i64 %x) nounwind ssp {
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entry:
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; CHECK: inv_64
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; CHECK: mvn x0, x0
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; CHECK: ret
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%inv = xor i64 %x, -1
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ret i64 %inv
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}
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; Multiplying by a power of two plus or minus one is better done via shift
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; and add/sub rather than the madd/msub instructions. The latter are 4+ cycles,
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; and the former are two (total for the two instruction sequence for subtract).
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define i32 @f0(i32 %a) nounwind readnone ssp {
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; CHECK-LABEL: f0:
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; CHECK-NEXT: add w0, w0, w0, lsl #3
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; CHECK-NEXT: ret
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%res = mul i32 %a, 9
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ret i32 %res
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}
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define i64 @f1(i64 %a) nounwind readnone ssp {
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; CHECK-LABEL: f1:
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; CHECK-NEXT: lsl x8, x0, #4
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; CHECK-NEXT: sub x0, x8, x0
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; CHECK-NEXT: ret
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%res = mul i64 %a, 15
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ret i64 %res
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}
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define i32 @f2(i32 %a) nounwind readnone ssp {
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; CHECK-LABEL: f2:
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; CHECK-NEXT: lsl w8, w0, #3
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; CHECK-NEXT: sub w0, w8, w0
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; CHECK-NEXT: ret
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%res = mul nsw i32 %a, 7
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ret i32 %res
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}
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define i64 @f3(i64 %a) nounwind readnone ssp {
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; CHECK-LABEL: f3:
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; CHECK-NEXT: add x0, x0, x0, lsl #4
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; CHECK-NEXT: ret
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%res = mul nsw i64 %a, 17
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ret i64 %res
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}
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